PTAB

IPR2016-00097

Micron Technology Inc v. Limestone Memory Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Clock Synchronous Semiconductor Memory Device
  • Brief Description: The ’296 patent discloses semiconductor memory devices with two main features. The first is an input circuit that can accommodate multiple external interface signals by using a plurality of selectively activatable input buffers of different types. The second is a low-power mode for a clock synchronous memory device that reduces current consumption by deactivating buffer circuits when the device is not being accessed.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1 and 11 under §102 over Nunomiya

  • Prior Art Relied Upon: Nunomiya (Patent 6,023,175).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Nunomiya, which discloses a "Level Interface Circuit," teaches every limitation of claims 1 and 11. Nunomiya describes a semiconductor device with two parallel level interface circuits (IF1 for LVTTL, IF2 for SSTL) that function as a "plurality of input buffers of different types or configurations." These buffers are coupled to a common internal output node (OUT). Nunomiya also discloses a determination circuit that acts as "program circuitry," generating a signal (n10) to set one of the input buffers to an operable state, which then drives the internal node based on a received external signal (IN). Dependent claim 11 is met because Nunomiya’s received signal IN is explicitly described as being "externally input."

Ground 2: Obviousness of Claim 12 under §103 over Nunomiya in view of Yukshing

  • Prior Art Relied Upon: Nunomiya (Patent 6,023,175) and Yukshing (Patent 5,848,014).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Nunomiya teaches all elements of claim 12 except for specifying that the control signal activating the input buffers is an internal control signal. Nunomiya discloses an enable signal (EN) that activates the buffers but is silent on whether it is internal or external. Yukshing, which discloses a low-power mode for SRAM, explicitly teaches an internal control signal (CONTROL) generated by a sleep control circuit to disable and enable input buffers.
    • Motivation to Combine: A POSITA would combine these references because both teach techniques for creating input circuits, and the control signals in both patents (EN in Nunomiya, CONTROL in Yukshing) serve the identical function of controlling the operability of input buffers. Petitioner argued it would have been a simple substitution of one known element for another to achieve predictable results, particularly given market incentives to reduce power consumption. The ’296 patent itself describes using an internal control signal as a conventional design choice.
    • Expectation of Success: A POSITA would have had a high expectation of success because substituting Yukshing’s internal control signal for Nunomiya’s enable signal was a straightforward modification using known circuit design principles to achieve the predictable result of internal buffer control.

Ground 3: Obviousness of Claims 17-20 under §103 over Sakata in view of Yukshing

  • Prior Art Relied Upon: Sakata (Patent 6,339,344) and Yukshing (Patent 5,848,014).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sakata, which addresses power consumption in semiconductor devices, teaches most limitations of claims 17-20. Sakata discloses a buffer circuit, a clock buffer, and clock detection circuitry that generates a power-down signal (PWD) when a clock enable signal (CKE) is inactive for a prescribed time. This PWD signal deactivates the input buffer circuit. However, Sakata does not expressly teach deactivating the clock buffer or an activation control signal (like a chip select signal) in response to the power-down signal. Yukshing was argued to supply these missing elements, as it explicitly discloses disabling both input buffers and the clock buffer in response to a low-power sleep signal.
    • Motivation to Combine: A POSITA would combine Sakata and Yukshing because both address the identical technical problem of reducing current consumption in synchronous memory devices by disabling input circuitry in a low-power mode. Since Yukshing’s clock disable circuitry solves the same problem Sakata is directed to, a POSITA would have been motivated to incorporate Yukshing’s more comprehensive power-saving technique (disabling the clock buffer as well) into Sakata’s system.
    • Expectation of Success: The combination would yield predictable results, as the components from each reference (clock buffers, power-down signals, chip select signals) serve well-known, analogous functions in both patents. A POSITA would have recognized that applying Yukshing's clock buffer deactivation logic to Sakata's device was a known method to further reduce power consumption.

4. Key Claim Construction Positions

  • "plurality of input buffers of different types or configurations" (claims 1, 11, 12): Petitioner proposed this term means "two or more buffers each of which corresponds to a different interface or is of a different configuration." This construction was argued to be critical for the anticipation argument, as it allows Nunomiya's two interface circuits (LVTTL and SSTL) to meet the "different types or configurations" limitation, even if their circuit diagrams are similar, because they correspond to different interface standards. Petitioner supported this construction by citing the ’296 patent specification and its prosecution history, where the applicant distinguished prior art by emphasizing the ability to accommodate a plurality of interfaces.

5. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1, 11, 12, and 17-20 of the ’296 patent as unpatentable.