PTAB

IPR2016-00144

Xilinx Inc v. QuickcoMPIle IP LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System for Programming a Field Programmable Gate Array
  • Brief Description: The ’699 patent discloses a system that automatically converts a user-defined algorithm, specified in a high-level source code, into a bitstream for programming a Field Programmable Gate Array (FPGA). The system utilizes an analyzer to identify vector processing operations within the source code and a mapper to translate those operations onto the FPGA’s physical logic components.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 6 are obvious over Banerjee in view of Benkrid

  • Prior Art Relied Upon: Banerjee (a 2000 IEEE Symposium paper on a MATLAB compiler for reconfigurable systems) and Benkrid (a 2001 IEEE Symposium paper on high-level programming for FPGAs).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Banerjee’s MATCH Compiler system teaches the core elements of independent claim 1. The MATCH system analyzes a high-level language (MATLAB) designed to process vectors, identifies vector processing operations by parsing the code, maps these operations to hardware components using predefined MATLAB libraries, and generates configuration bitstreams to program an FPGA. For dependent claim 6, Benkrid’s disclosure of a “library of hardware skeletons for common image processing tasks,” including arithmetic and logical operations, was argued to teach the claimed library of predefined functions.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the references because both address programming Xilinx FPGAs for image processing. Petitioner asserted a POSITA would apply the known technique from Benkrid—developing and organizing a hardware skeleton library—to the compiler system of Banerjee to improve its image processing capabilities and yield the predictable result of a more structured, application-oriented programming model.
    • Expectation of Success: The combination involved applying a known library framework to a compatible compiler system, a straightforward integration with a high expectation of success.

Ground 2: Claims 2, 4, and 5 are obvious over Banerjee and Benkrid in view of Haldar

  • Prior Art Relied Upon: Banerjee, Benkrid, and Haldar (a 2000 conference paper on scheduling algorithms for designs described in MATLAB).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground adds Haldar to address dependent claims related to the analyzer’s functions. Petitioner argued that Haldar, whose authors overlap with Banerjee and which describes the same MATCH compiler, provides specific implementation details. Haldar teaches constructing a dataflow graph from an abstract syntax tree and performing dependency analysis to enable pipelining. This process inherently determines the relative timing between operations (claim 2), identifies operator types and operands (claim 4), and identifies the orders and dependencies between operations (claim 5).
    • Motivation to Combine: A POSITA would look to Haldar for its detailed teachings on the inner workings of the MATCH compiler to better understand and implement the system disclosed in Banerjee. As Haldar directly addresses generating a data flow graph to ensure proper sequencing and timing, its combination with Banerjee was presented as a logical step for implementing the compiler effectively.

Ground 3: Claim 3 is obvious over Banerjee, Benkrid, and Haldar in view of Hammes

  • Prior Art Relied Upon: Banerjee, Benkrid, Haldar, and Hammes (a 1999 conference paper on high-level language compilation).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground adds Hammes to further detail the creation of a dataflow graph. Petitioner contended that Hammes, which describes the “Cameron Project” explicitly cited by Banerjee, teaches constructing a hierarchical Data Dependence and Control Flow (DDCF) graph. This DDCF graph is designed to expose data dependencies and show the interrelationships between high-level constructs, thereby indicating the "overall flow of vector processing results between vector operations" as required by claim 3.
    • Motivation to Combine: A POSITA would have been motivated to consult and combine the teachings of Hammes because both references are in the same field of high-level compilation, both deal with data flow graphs, and Banerjee explicitly cites the project described in Hammes. This combination would allow for a predictable approach to programming FPGAs with complete algorithms by using a data flow graph that specifies the overall processing flow.

Ground 4: Claims 7-10 are obvious over Banerjee and Benkrid in view of AAPA

  • Prior Art Relied Upon: Banerjee, Benkrid, and Applicants Admitted Prior Art (AAPA) from the specification of the ’699 patent itself.
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addresses claims related to using rule sets and optimizing device layout. Petitioner argued that the AAPA explicitly admits that it was "well-known" in the art to provide library elements that reflect FPGA architecture features, including timing and power constraints (claim 7). The AAPA also admits the use of "well-known programs" and algorithms that evaluate a "variety of different approaches" to component placement to find the one with the "densest floor space" (claims 9 and 10). Accessing these rules via lookup tables or parametric tools was also described as known (claim 8).
    • Motivation to Combine: A POSITA would apply the well-known techniques described in the AAPA to the Banerjee/Benkrid system to achieve predictable results. The motivation was to improve the known compiler system by incorporating established methods for ensuring that timing, power, layout, and area requirements are properly met for a given FPGA architecture, which is a standard goal in the field.

4. Key Claim Construction Positions

  • Petitioner argued that the four primary limitations of independent claim 1 are means-plus-function limitations governed by 35 U.S.C. §112, ¶6.
  • For each "means for" limitation (analyzing, identifying, mapping, and programming), Petitioner identified the specific function recited in the claim.
  • The corresponding structure disclosed in the ’699 patent specification was identified as the computer-implemented algorithms and components—specifically the analyzer, mapper, and conventional bit stream generator—that perform the recited functions, as well as their equivalents. This construction was central to mapping the prior art, which disclosed similar algorithmic structures performing the same functions.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-10 of the ’699 patent as unpatentable.