Sony Corp v. Raytheon Co

1. Case Identification

• Case #: IPR2016-00209
• Patent #: 5,591,678
• Filed: 2015-11-18
• Petitioner(s): Sony Corporation
• Patent Owner(s): Raytheon Company
• Challenged Claims: 1-18

2. Patent Overview

• Title: Method of fabricating stacked integrated circuits
• Brief Description: The ’678 patent discloses a method for manufacturing stacked integrated circuits by transferring a thin microelectronic circuit element from a thick, handleable first substrate to a second substrate. The method involves furnishing a first substrate with three layers (an etchable layer, an etch-stop layer, and a wafer), forming a circuit on the wafer, attaching the wafer to a second substrate for support, and then chemically etching away the original thick etchable layer to expose the back side of the circuit for connections.

3. Grounds for Unpatentability

Ground 1: Anticipation over Liu - Claims 1-4, 6, 7, 10, and 11 are anticipated by Liu

• Prior Art Relied Upon: Liu (Patent 4,422,091).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Liu taught every limitation of the challenged claims. Liu described a method for fabricating a charge-coupled device (CCD) that mirrored the process of the ’678 patent. This included furnishing a three-part substrate with an etchable layer (GaAs substrate 18), an etch-stop layer ("window layer" 4), and a wafer (layers 6 and 8). Liu then disclosed forming a CCD circuit on the wafer, attaching the wafer to a second support substrate, and subsequently etching away the original etchable layer down to the etch-stop layer using a selective liquid etchant. Liu also disclosed the dependent claim features, such as patterning the etch-stop layer to form electrical connections and using a second substrate that contains its own microelectronic circuit.

Ground 2: Obviousness over Liu and Black - Claims 2-4 and 11 are obvious over Liu in view of Black

• Prior Art Relied Upon: Liu (Patent 4,422,091), Black (Patent 4,426,768).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that while Liu anticipated the claims related to patterning the etch-stop layer, its disclosure focused on patterning at the periphery of the device. If the Board found this insufficient, Black supplied the missing element by explicitly teaching the patterning of an etch-stop layer to form "windows" inward from the device edge. This patterning in Black exposed underlying bonding pads for electrical connections, directly corresponding to the "vias" described in the ’678 patent.
  • Motivation to Combine: A POSITA would combine Black's inward patterning with Liu's fabrication process to achieve well-known and predictable benefits. These benefits included the ability to place more contacts by using the center of the substrate, accessing centrally located circuit elements, and protecting contacts from edge damage. Applying Black’s known technique to Liu’s analogous process was a simple design choice.
  • Expectation of Success: A POSITA would have a high expectation of success, as the combination merely involved changing the location of a known patterning technique without altering the fundamental substrate transfer and etching process.

Ground 3: Obviousness over Liu and Riseman - Claims 5 and 12-16 are obvious over Liu in view of Riseman

• Prior Art Relied Upon: Liu (Patent 4,422,091), Riseman (Patent 4,106,050).
• Core Argument for this Ground:
  • Prior Art Mapping: These claims added limitations specifying the substrate materials: a silicon etchable layer, a silicon dioxide (SiO2) etch-stop layer, and a single-crystal silicon wafer. Petitioner argued that while Liu disclosed the general process, Riseman taught using this exact material combination in a nearly identical fabrication method. Riseman explicitly disclosed an integrated circuit structure with a silicon etchable layer, an SiO2 etch-stop layer, and a single-crystal silicon wafer, and described removing the silicon layer down to the SiO2 layer.
  • Motivation to Combine: A POSITA would have been motivated to implement Liu’s process using the specific materials taught by Riseman. Liu’s disclosure was not limited to GaAs and suggested other semiconductors could be used. The silicon/SiO2 system was the dominant, most stable, and best-understood material combination for semiconductor manufacturing at the time. A POSITA would have recognized it as a preferred and obvious choice for Liu’s method.
  • Expectation of Success: Success would be expected, as the combination involved applying a standard, industry-leading material set to a known fabrication process, which would yield predictable results.
• Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations including Liu with Oldham (for epoxy degassing/curing steps), Wen (for further etching details), Wen and Ying (for using etching supports), and Riseman and Kusunoki (for specific layer thicknesses).

4. Key Claim Construction Positions

• "Microelectronic Circuit Element": Petitioner argued this term should be interpreted broadly, consistent with the patent’s specification, to mean "active devices or passive structures useful for circuits." This broad construction was central to the argument that the prior art, which disclosed elements like CCDs, transistors, and patterned conductors, met this claim limitation.
• "Etchable Layer" and "Etch-Stop Layer": Petitioner proposed that these terms be defined by their relative etch rates in a particular etchant, where the "etchable layer" dissolves rapidly and the "etch-stop layer" dissolves slowly or not at all. This construction was key to mapping the function of corresponding layers in the prior art.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that review should not be discretionarily denied based on a previously filed IPR petition (IPR2015-01201) involving the same patent. The petition asserted that the challenges presented were not redundant because the current petition did not rely on the principal prior art references cited in the earlier petition, thus presenting new grounds for unpatentability.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-18 of Patent 5,591,678 as unpatentable.