Micron Technology Inc v. Innovative Memory Systems Inc

1. Case Identification

• Case #: IPR No. Unassigned
• Patent #: 6,169,503
• Filed: December 14, 2015
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Innovative Memory Systems, Inc.
• Challenged Claims: 1, 8-10

2. Patent Overview

• Title: Programmable Arrays for Data Conversions Between Analog and Digital
• Brief Description: The ’503 patent relates to analog-to-digital (A/D) converters. The invention purports to reduce the physical size of A/D converters by replacing traditional resistor-based comparators with an array of programmable reference cells, such as floating-gate transistors, each having a different, programmable threshold voltage.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claim 1 under 35 U.S.C. §102

• Prior Art Relied Upon: Seligson (Patent 5,376,935).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Seligson discloses every element of claim 1. Seligson teaches an A/D converter that uses a plurality of programmable floating-gate transistors (62a-h) with different, programmable threshold voltages. An analog input signal is applied to the gates of these transistors, and an encoder generates a multi-bit digital output based on which transistors conduct. Petitioner contended that Seligson’s disclosure of a row of reference transistors within a larger matrix of memory cells satisfies the claim limitation of "an array of memory cells that contain the plurality of transistors."

Ground 2: Obviousness of Claim 8 under 35 U.S.C. §103

• Prior Art Relied Upon: Seligson (Patent 5,376,935) in view of Bucklen (Patent 4,591,825).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that while Seligson discloses the core components of claim 8—an A/D converter with an "array of reference cells," a "sense circuit," and an "encoder"—it does not explicitly detail the encoder's internal mechanism. Bucklen was introduced to supply this missing element. Bucklen teaches a well-known encoding technique for A/D converters where an adder is used to count the logical outputs from the comparators (the "thermometer code") to generate the final binary output. This directly teaches the limitation "wherein the encoder comprises a counter coupled to count pulses from the sense circuit."
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings because Seligson produces a standard thermometer code output that requires encoding. Bucklen provides a simple, conventional, and known technique for doing so. Applying Bucklen’s counting method to Seligson's converter was described as a common-sense implementation to achieve a functional encoder.
  • Expectation of Success: A POSITA would have a high expectation of success, as the combination involves applying a standard encoding module to a standard converter output to achieve a predictable result.

Ground 3: Obviousness of Claims 9-10 under 35 U.S.C. §103

• Prior Art Relied Upon: Seligson (Patent 5,376,935) in view of Yonemaru (Patent 5,187,483).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that claims 9 and 10 are obvious by modifying Seligson's single-row converter with the multi-row architecture taught by Yonemaru. Claim 9 adds limitations for an array containing a "plurality of rows" and a "row decoder" for selecting a row. Claim 10 further adds a "terminal for a conversion select signal" that provides an address to the row decoder. Yonemaru explicitly teaches a multi-row, serial-to-parallel converter where an upper-bit encoder acts as a row decoder, using address signals (SE0-SE3) to select specific rows of reference components to convert different ranges of analog values.
  • Motivation to Combine: A POSITA would be motivated to modify Seligson's design with Yonemaru's multi-row architecture to gain the known advantage of handling different analog signal ranges, a fundamental objective in A/D converter design. This would involve arranging Seligson's reference cells into multiple rows and adding the row selection logic from Yonemaru.
  • Expectation of Success: The combination was presented as a predictable integration of known circuit architectures to add functionality, with a high likelihood of success.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including for claim 1 over Seligson and Yonemaru, and for claim 8 over Seligson, Bucklen, and Yonemaru, relying on similar motivations to combine existing technologies to achieve predictable improvements.

4. Key Claim Construction Positions

• "array" (claims 1, 8-10): Petitioner argued for the construction "two or more elements that form at least one of a row or column." This construction is central to the anticipation argument, as the primary reference Seligson explicitly discloses a single row of reference transistors. Petitioner contended this construction is supported by the patent's own use of "array" for single-row embodiments and by claim 9's language, which would be redundant if "array" inherently meant multiple rows.
• "a counter coupled to count pulses from the sense circuit" (claim 8): Petitioner proposed this term means "a counter that counts changes in current or voltage from a circuit that indicates whether a given reference cell is conducting." This construction was argued to align with the well-known technique of counting thermometer code bits, directly linking the claim language to the teachings of the secondary reference, Bucklen, which discloses an adder for this purpose.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1, 8, 9, and 10 of Patent 6,169,503 as unpatentable.