PTAB

IPR2016-00323

Micron Technology Inc v. Innovative Memory Systems Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System for Configuring Compensation
  • Brief Description: The ’953 patent discloses a non-volatile storage system designed to reduce data errors caused by electric field "coupling" between adjacent floating gates in memory cells. The system uses a managing circuit that can be configured to selectively compensate for this coupling effect either during a read operation or during a programming operation, but not necessarily both, to improve data integrity.

3. Grounds for Unpatentability

Ground 1: Obviousness over Chen in view of Harari - Claims 1, 2, 8, and 9 are obvious over Chen in view of Harari.

  • Prior Art Relied Upon: Chen (Patent 5,867,429) and Harari (Patent 5,297,148).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Chen taught all elements of the challenged claims except for the selective configuration of compensation. Chen disclosed a non-volatile memory system with a managing circuit that compensates for floating-gate coupling during both read operations and program-verify steps. Crucially, Chen explicitly identified a key disadvantage of its method: it increases the time needed for read and program operations, thus degrading performance. Harari addressed an analogous performance problem by teaching an adaptive error correction system where an advanced, time-consuming error correction scheme is selectively enabled only when necessary (i.e., upon detection of a "hard error"), thereby minimizing performance impact while maintaining reliability. The combination of Chen's compensation system with Harari's selective enablement strategy rendered the claims obvious.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references for several reasons. First, Chen expressly incorporated Harari by reference, directing a POSITA to its teachings. Second, both patents addressed the same field of non-volatile memory and sought to improve reliability. A POSITA, recognizing the performance degradation problem explicitly stated in Chen, would have been motivated to apply the known technique of selective enablement taught by Harari to solve this known problem and achieve the predictable result of improved performance.
    • Expectation of Success: A POSITA would have had a high expectation of success in applying Harari's selective control logic to Chen's compensation system. The combination involved applying a known control strategy to a known system to mitigate a known problem, which would have been a straightforward design choice.

Ground 2: Obviousness over Chen in view of Fong and Harari - Claims 1, 2, 8, and 9 are obvious over Chen in view of Fong and Harari.

  • Prior Art Relied Upon: Chen (Patent 5,867,429), Fong (Patent 7,230,851), and Harari (Patent 5,297,148).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative or supplemental combination. Petitioner asserted that Chen taught read compensation while Fong taught a distinct method for program compensation. Specifically, Fong disclosed compensating for coupling during programming by adjusting and compressing the threshold voltages of the memory states. Like Chen, Fong also explicitly acknowledged that its compensation technique had a performance drawback, as it could "slow down operation of the memory device." Harari, as in Ground 1, provided the teaching of selectively enabling such performance-impacting techniques only when needed.
    • Motivation to Combine: A POSITA would combine Chen and Fong to create a comprehensive system that compensates for floating-gate coupling during both read and program operations. Given that both Chen and Fong disclosed that their respective techniques negatively impacted performance, it would have been an obvious design choice to incorporate Harari's adaptive, selective-use methodology. This three-way combination would apply Harari's control scheme to the combined read/program compensation techniques of Chen and Fong to minimize the known performance penalties of each.
    • Expectation of Success: A POSITA would have expected success in combining these complementary techniques. The integration involved using known compensation methods for different operational phases (read vs. program) and applying a well-understood control strategy (selective enablement) to optimize performance, representing a predictable application of known principles.

4. Key Claim Construction Positions

Petitioner argued that the following claim terms, under the broadest reasonable interpretation standard, were central to its unpatentability arguments:

  • "managing circuit" (claims 1, 2, 8, 9): Proposed as "one or more components to control reading and programming operations," including elements like control circuitry, a state machine, decoders, and a controller. This broad construction allowed Petitioner to map the control functions described across the prior art references to this limitation.
  • "host" (claim 2): Proposed as "an electronic device." This construction was based on examples in the ’953 patent's specification (e.g., digital camera, music player) and was important for mapping Chen's disclosure of a memory system connected to a "host computer."
  • "multi-state flash memory devices" (claim 9): Proposed as "flash memory devices with cells that store multiple bits of digital data." This construction was critical for mapping prior art like Chen, which explicitly taught memory cells storing two or more bits of data per cell.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1, 2, 8, and 9 of the ’953 patent as unpatentable under 35 U.S.C. §103.