PTAB

IPR2016-00322

Micron Technology Inc v. Innovative Memory Systems Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Use of Voids Between Elements in Semiconductor Structures for Isolation
  • Brief Description: The ’849 patent discloses a non-volatile memory cell array that uses voids within the dielectric material separating adjacent memory cell stacks. The voids, having a lower dielectric constant than solid material, are intended to reduce parasitic capacitive coupling and electric field interference, particularly in tightly packed semiconductor structures.

3. Grounds for Unpatentability

Ground 1: Claims 1-6 are obvious over Takeuchi in view of Lee

  • Prior Art Relied Upon: Takeuchi (Patent 6,720,612) and Lee (a 2002 journal article, "Effects of Floating Gate Interference on NAND Flash Memory Cell Operation").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Takeuchi disclosed a NAND flash memory array with most of the claimed features, including the formation of voids or cavities within an insulating film between adjacent memory cell gates to reduce capacitive coupling. Takeuchi recognized that voids are more easily formed when using a high aspect ratio (cell height to gate spacing). However, Petitioner contended that Takeuchi was silent on whether the control gates extend downward between adjacent floating gates (a limitation of claim 1) and did not explicitly disclose the specific high aspect ratios recited in the claims (e.g., spacing less than one-fifth of the structure's thickness). Lee was introduced to supply these elements, as it disclosed a conventional NAND array where control gates extend downward between adjacent floating gates to provide shielding and described fabricating memory cells with gate-to-gate spacing (e.g., 0.12 µm) that would meet the claimed aspect ratios when applied to the structures disclosed in Takeuchi.
    • Motivation to Combine: A POSITA would combine Takeuchi and Lee as both addressed the identical, well-known problem of parasitic capacitance in scaled-down NAND flash memory arrays and proposed a similar solution involving air gaps. Given the industry-wide pressure to increase memory density, a POSITA would have looked to known techniques for reducing gate-to-gate spacing, such as those described in Lee, and applied them to Takeuchi's design. Furthermore, implementing Lee's downward-extending control gate structure in Takeuchi's array would be a known method to improve shielding, a motivation admitted in the ’849 patent's own background section.
    • Expectation of Success: Combining these references involved applying known design choices and fabrication techniques to achieve predictable improvements in device performance and density. A POSITA would have had a reasonable expectation that reducing the gate spacing in Takeuchi's device according to Lee's teachings would successfully achieve a higher aspect ratio and improved isolation.

Ground 2: Claims 1-6 are obvious over Sato in view of Lee

  • Prior Art Relied Upon: Sato (JP Application # 2000-100976) and Lee (the same 2002 journal article).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Sato, like Takeuchi, taught solving the capacitive coupling problem by providing a cavity or void within the insulating film between adjacent memory cells. Sato also disclosed control gates extending downward between adjacent floating gates. However, Petitioner argued that Sato did not expressly disclose the claimed high aspect ratios or the specific NAND configuration required by claim 2 (where charge storage elements form series strings). Lee was again relied upon to supply these missing features. Lee taught the claimed NAND configuration and disclosed gate-to-gate spacing dimensions that, when combined with the cell heights described in Sato, would result in aspect ratios meeting the claim limitations (e.g., greater than 5:1 and 8:1).
    • Motivation to Combine: A POSITA would combine Sato and Lee because they shared a common goal of mitigating interference in dense memory arrays. A POSITA would have been motivated by market pressures for mass storage to arrange Sato's floating-gate cells into the well-known NAND array configuration taught by Lee. This would be a simple substitution of one known array architecture for another to achieve the predictable benefits of high-density storage. Applying Lee's reduced gate spacing to Sato's structures would be an obvious path to further increase density and enhance the formation of the insulating voids taught by Sato.
    • Expectation of Success: A POSITA would expect success from this combination, as arranging EEPROM cells in a NAND configuration was a standard technique for mass storage devices. Modifying the dimensions of Sato's cells based on the predictable design principles outlined in Lee to achieve a higher aspect ratio would have yielded the expected result of improved electrical isolation.

4. Key Claim Construction Positions

  • "thickness" (claims 1-6): Petitioner argued that "thickness" should be construed to mean "the height as measured from the substrate." This proposed construction was based on the specification's interchangeable use of the terms "thickness" and "height" to describe the vertical dimension of the memory cell stacks. This construction was critical to Petitioner's obviousness arguments, as it defined the vertical component of the aspect ratio (height-to-spacing) that Petitioner alleged was rendered obvious by the prior art combinations.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-6 of Patent 7,045,849 as unpatentable.