PTAB

IPR2016-00394

Micron Technology Inc v. Elm 3DS Innovations LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’617 patent discloses three-dimensional (3D) integrated circuit structures and methods for their fabrication. The technology focuses on stacking thinned semiconductor substrates and using low-stress dielectric materials to manage mechanical stress that accumulates in multi-layered devices.

3. Grounds for Unpatentability

Ground 1: Obviousness over Bertin, Poole, and Leedy ’695 - Claims 36 and 51 are obvious over Bertin in view of Poole and Leedy ’695.

  • Prior Art Relied Upon: Bertin (Patent 5,202,754), Poole (Patent 5,162,251), and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bertin taught the foundational structure of a 3D multichip package with stacked semiconductor chips, thinned substrates (to 20 µm or less), and vertical through-silicon interconnects insulated by oxidized sidewalls. However, Bertin did not explicitly teach polishing the thinned substrate or that its insulating dielectrics were "low stress." Poole was introduced to supply the teaching of a two-step thinning process for semiconductor substrates that includes polishing to create a smooth, planar surface. Leedy ’695, which the ’617 patent incorporates by reference, was introduced to teach the use of low-stress silicon oxide and silicon nitride dielectrics to insulate interconnects, thereby increasing structural integrity and durability.
    • Motivation to Combine: A POSITA would combine Bertin and Poole because thinning and polishing are standard, complementary steps to create substrates suitable for reliable bonding in 3D stacks. A POSITA would combine this with Leedy ’695 because managing mechanical stress is a critical, known problem in 3D ICs. Substituting Bertin's standard oxide with Leedy's well-characterized low-stress dielectric was presented as a predictable solution to improve device yield and reliability, an express goal of Leedy ’695.
    • Expectation of Success: Petitioner asserted a high expectation of success, as the combination involved substituting known substrate preparation techniques (Poole) and known insulating materials (Leedy ’695) into a known 3D architecture (Bertin) to achieve their predictable benefits.

Ground 2: Obviousness over Yu and Leedy ’695 - Claims 36 and 51 are obvious over Yu in view of Leedy ’695.

  • Prior Art Relied Upon: Yu (a 1996 IEEE conference paper titled "Real-Time Microvision System with Three-Dimensional Integration Structure") and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Yu disclosed a 3D integrated circuit system with vertically stacked 2D LSIs (Large Scale Integration circuits). Yu explicitly taught grinding and polishing silicon substrates to a thinness of about 30 µm and bonding them with microbumps and adhesive. Yu further disclosed buried interconnects insulated with silicon dioxide (SiO₂). The primary missing element, Petitioner argued, was the explicit disclosure that this SiO₂ insulator was a "low stress" dielectric as required by the claims.
    • Motivation to Combine: A POSITA would combine Yu with Leedy ’695 because both address the same technological field of 3D IC integration. Leedy ’695's express purpose was to provide low-stress dielectrics to enhance structural integrity and prevent stress-related failures like cracking and warpage, which are inherent challenges in the stacked structures described by Yu. The motivation was to improve the robustness and manufacturability of Yu’s system by applying the known stress-reduction solution from Leedy ’695.
    • Expectation of Success: Success would be reasonably expected because Leedy ’695 taught that its low-stress films were compatible with conventional IC processing techniques. Applying Leedy's known deposition process for low-stress SiO₂ in place of Yu's standard SiO₂ was argued to be a straightforward substitution of one known element for another to obtain a predictable improvement.

4. Key Claim Construction Positions

Petitioner argued that the term "substantially flexible" required specific construction based on the patentee's lexicography and statements during prosecution to avoid being found indefinite. Two constructions were proposed depending on the type of "substrate" being modified:

  • "substantially flexible" semiconductor substrate: Petitioner proposed this term be construed as "a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." This construction was based on an explicit definition provided in the ’617 patent specification.
  • "substantially flexible" circuit substrate: Petitioner proposed this term be construed as "an integrated circuit [circuit substrate] having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5×10⁸ dynes/cm² tensile or less." This construction was based on definitions and arguments the applicant made during the prosecution of related patent applications to overcome prior art.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 36 and 51 of Patent 8,410,617 as unpatentable.