PTAB

IPR2016-00687

Samsung Electronics Co Ltd v. Elm 3DS Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’119 patent discloses methods for fabricating three-dimensional (3D) integrated circuits (ICs), particularly stacked memory devices. The technology involves thinning semiconductor substrates to make them flexible, bonding them into a vertical stack, and forming vertical interconnections through the substrates.

3. Grounds for Unpatentability

Ground 1: Claims 1, 7, and 17-18 are obvious over Bertin, Poole, and Leedy '695

  • Prior Art Relied Upon: Bertin (Patent 5,202,754), Poole (Patent 5,162,251), and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bertin taught a 3D multichip package with densely stacked semiconductor chips, vertical through-substrate interconnects, and dielectric layers, meeting most limitations of the independent claims. However, Bertin used a wet etching process for thinning and did not explicitly disclose polishing or the use of low-stress dielectrics. Poole was cited for its two-step process of grinding and then polishing a substrate to a thickness of 10 µm, resulting in a smooth surface. Leedy ’695 was cited for its disclosure of fabricating flexible ICs using very thin low-stress dielectric materials (e.g., silicon dioxide or silicon nitride) to improve structural integrity.
    • Motivation to Combine: A POSITA would combine Bertin with Poole to replace Bertin’s wet etching with a simpler, well-known grinding and polishing process that achieves a planar, defect-free surface ideal for stacking. A POSITA would combine the resulting structure with the teachings of Leedy ’695 because both Bertin and Leedy ’695 aimed to improve high-density 3D ICs. Incorporating Leedy ’695’s low-stress dielectrics would predictably address the known problem of stress management and improve the structural integrity of Bertin’s stacked device.
    • Expectation of Success: The combination was argued to be predictable. Poole’s thinning process was a well-known alternative to wet etching. Leedy ’695 explained its low-stress dielectrics were versatile and could be deposited using common techniques like plasma-enhanced chemical vapor deposition (PECVD), making them a straightforward substitute for the conventional dielectrics in Bertin.

Ground 2: Claim 33 is obvious over Bertin, Poole, Leedy '695, and Ludwig

  • Prior Art Relied Upon: Bertin (Patent 5,202,754), Poole (Patent 5,162,251), Leedy ’695 (Patent 5,354,695), and Ludwig (Patent 5,581,498).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1 to meet the additional limitations of claim 33, which required that one of the stacked ICs comprise a logic circuit and others comprise memory circuits (specifically DRAM). While the base combination taught a stack of memory circuits (DRAM as disclosed in Bertin), it did not explicitly teach a dedicated, separate logic circuit within the stack. Ludwig was introduced because it taught a stacked IC system comprising a stack of DRAM memory chips and a separate, dedicated logic chip (a "VIC chip") that provides interface circuitry, buffering, decoding, and memory refresh functions for the entire stack.
    • Motivation to Combine: Petitioner argued a POSITA would be motivated to integrate Ludwig’s VIC chip into the Bertin-based stack. Both Bertin and Ludwig addressed the challenges of 3D IC integration. Ludwig’s design solved the known problem of how to make a dense stack of memory chips compatible with existing host systems. A POSITA would have recognized the benefit of adding Ludwig’s dedicated logic controller to Bertin’s memory stack to manage its operation efficiently.
    • Expectation of Success: The result of the combination would have been predictable, as it amounted to substituting one of Bertin’s memory chips with Ludwig’s specialized logic chip to provide a known function (control and refresh) for the remaining memory chips.

Ground 3: Claims 1, 7, and 17-18 are obvious over Hsu and Leedy '695

  • Prior Art Relied Upon: Hsu (Patent 5,627,106) and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner presented this as an alternative to Ground 1, with Hsu serving as the primary reference for the stacked IC structure. Hsu was argued to teach a method of connecting 3D ICs by stacking a master chip and subordinate chips. Hsu disclosed grinding and polishing the substrate to a thin dimension and forming vertical interconnects through it. Similar to Bertin, Hsu disclosed a dielectric layer (silicon dioxide film) but did not explicitly teach that it must be a low-stress dielectric. Leedy ’695 was again relied upon for its teachings on using low-stress dielectrics to enhance structural integrity in flexible ICs.
    • Motivation to Combine: The motivation was analogous to Ground 1. Both Hsu and Leedy ’695 were directed to improving high-density, 3D integrated circuits. A POSITA would have been motivated to apply the known stress-reduction techniques from Leedy ’695 to Hsu’s stacked structure to improve its reliability and manufacturability, which are critical for such devices.
    • Expectation of Success: Success would have been reasonably expected because Leedy ’695’s techniques for depositing low-stress silicon dioxide were a known improvement over the standard deposition methods used in Hsu, offering a predictable way to enhance the structural properties of the final device.
  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Hsu, Leedy ’695, and Ludwig for claim 33. Alternative grounds were also presented that replaced Leedy ’695 with Kowa (Japanese Publication H3-151637) for its teachings on stress-balancing dielectric films, and grounds that omitted Leedy ’695 and Kowa entirely based on alternative claim constructions.

4. Key Claim Construction Positions

  • "substantially flexible monocrystalline semiconductor substrate": Petitioner argued this term, as used in claim 1, should be construed as "a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." This construction was based on the patent’s specification, which Petitioner asserted acted as its own lexicographer by explicitly defining the term this way. Further support was drawn from statements made during the prosecution of related patents to overcome indefiniteness rejections.
  • "substantially flexible integrated circuits": Petitioner argued this separate term from claim 1 requires more than just thinning. The proposed construction was "an integrated circuit having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5×10⁸ dynes/cm² tensile or less." This construction was based on specification statements linking flexibility to both thinness and the use of low-stress dielectrics, as well as arguments made during prosecution of related applications to distinguish prior art.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 7, 17-18, and 33 of the ’119 patent as unpatentable.