PTAB

IPR2016-00786

Samsung Electronics Co Ltd v. Elm 3DS Innovations LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Three Dimensional Structure Memory
  • Brief Description: The ’570 patent discloses fabrication methods for three-dimensional integrated circuits (3D ICs). The technology involves thinning semiconductor substrates to make them flexible, stacking multiple circuit layers, and forming vertical interconnections (vias) between the layers to increase device density and performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Bertin, Poole, and Leedy '695 - Claims 58, 60, 61, and 67 are obvious over Bertin in view of Poole and Leedy '695.

  • Prior Art Relied Upon: Bertin (Patent 5,202,754), Poole (Patent 5,162,251), and Leedy '695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bertin taught a 3D multichip package with stacked ICs thinned to approximately 20 µm and featuring vertical interconnects, meeting most limitations of independent claim 58. However, Bertin’s thinning process involved wet etching without explicitly teaching polishing, and its dielectric layers were not described as having low stress. To supply these missing elements, Petitioner cited Poole, which taught a well-known two-step grinding and chemical mechanical polishing (CMP) process for thinning silicon substrates to 10 µm to create a highly planar and smooth surface. Petitioner also cited Leedy '695, which taught the fabrication of flexible ICs using low tensile stress dielectrics (e.g., silicon dioxide with stress < 5x10⁸ dynes/cm²) to improve structural integrity.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Poole with Bertin to replace Bertin’s wet etching with a simpler, more effective thinning and polishing method. This combination would predictably achieve the thin, planar substrate essential for reliable bonding and interconnects in a stacked structure, while simplifying manufacturing. A POSITA would combine Leedy '695 with Bertin to address the known problem of mechanical stress in 3D ICs. Substituting Leedy’s low-stress dielectric for Bertin’s standard dielectric was a known technique to improve the structural integrity and reliability of the final device.
    • Expectation of Success: A POSITA would have a reasonable expectation of success, as the combination involved substituting known, compatible processes (Poole's polishing, Leedy's dielectric deposition) into a conventional 3D IC fabrication flow (Bertin) to achieve predictable improvements in manufacturability and device reliability.

Ground 2: Obviousness over Hsu and Leedy '695 - Claims 58, 60, 61, and 67 are obvious over Hsu in view of Leedy '695.

  • Prior Art Relied Upon: Hsu (Patent 5,627,106) and Leedy '695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Hsu taught a method for connecting 3D ICs, including a "master chip" and a "subordinate chip" stacked together with vertical interconnects. Hsu explicitly disclosed grinding and polishing the substrate to leave only a thin portion remaining. However, Hsu did not disclose that its silicon dioxide insulating film constituted a "low-stress" dielectric as required by the claims (under Petitioner’s construction). As in Ground 1, Leedy '695 was relied upon to teach the benefits and methods of using low tensile stress dielectrics to create durable, flexible IC structures.
    • Motivation to Combine: A POSITA would be motivated to combine Leedy '695 with Hsu to improve a known 3D IC structure by incorporating a known solution (low-stress dielectrics) to the well-understood problem of mechanical stress. Both references were directed to improving high-density integrated circuits, making Leedy '695 a natural and logical source for a POSITA seeking to enhance the reliability and yield of Hsu's stacked device.
    • Expectation of Success: A POSITA would reasonably expect success in substituting the low-stress dielectrics from Leedy '695 into Hsu’s process. Leedy taught deposition using common techniques like Plasma-Enhanced Chemical Vapor Deposition (PECVD), a straightforward alternative to the Atmospheric Pressure Chemical Vapor Deposition (APCVD) process described in Hsu. This combination would predictably yield a stacked IC with lower overall stress and improved durability.
  • Additional Grounds: Petitioner asserted alternative obviousness challenges for various claims under different proposed claim constructions. These grounds included combinations of Hsu and Kowa (Japanese Publication H3-151637) to teach stress balancing, Bertin and Poole alone, and Hsu alone.

4. Key Claim Construction Positions

Petitioner argued for specific constructions of the term "substantially flexible" based on the specification acting as a lexicographer and arguments made during prosecution of related patents, which gave rise to prosecution history estoppel.

  • "substantially flexible ... semiconductor substrate": Petitioner proposed the construction "a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." This definition was asserted to be explicitly provided in the specification and was used by the applicant to overcome indefiniteness rejections during prosecution of a related patent.
  • "substantially flexible" integrated circuit: Petitioner proposed the construction "an integrated circuit having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used... must have a stress of 5x10⁸ dynes/cm² tensile or less." Petitioner contended that for the entire circuit to be "flexible," the patentee linked this term not only to the substrate's physical thinness but also to the low-stress properties of the surrounding dielectric layers.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 58, 60, 61, and 67 as unpatentable.