PTAB

IPR2016-01178

Texas Instruments Inc v. Advanced Silicon Technologies LLC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Compressed Texture Caching in a Video Graphics System
  • Brief Description: The ’428 patent describes a video graphics texture mapping circuit designed to reduce memory bandwidth usage. The invention achieves this by storing compressed texture information in a dedicated on-chip cache, retrieving it from a main memory, and decompressing it only when needed for a texturing operation.

3. Grounds for Unpatentability

Ground I: Claims 1 and 2 are obvious over Griffin.

  • Prior Art Relied Upon: Griffin (Patent 5,880,737).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Griffin, which describes a graphics processing system consistent with Microsoft’s Talisman architecture, discloses every element of independent claim 1. Griffin’s shared memory (216) stores compressed texture information, and its compressed cache (416) stores a portion of that information. The combination of Griffin’s texture cache control (391), texture read queue (393), and command and memory control (380) collectively performs the functions of the claimed "texture address module," including determining if data is in the cache and copying it from memory if absent. Griffin’s decompression engine (404) decompresses the texture data, which is then used by the texture filter engine (403), satisfying the filtering block limitation of dependent claim 2.

Ground II: Claims 3, 4, and 25-29 are obvious over Griffin in view of Tarolli I.

  • Prior Art Relied Upon: Griffin (Patent 5,880,737) and Tarolli I (Patent 5,740,343).
  • Core Argument for this Ground:
    • Prior Art Mapping: Griffin was asserted to teach the base system of compressed texture caching, but only applies a single texture per pixel. Tarolli I, which teaches a texture compositing apparatus for combining multiple texture colors, provides the missing "blending block" functionality recited in claim 3. Petitioner argued that Tarolli I’s Texture Compositing Unit (TCU) would be operably coupled to Griffin’s filter engine (403) to combine the primary texture color with additional color values from a second texture. For claim 4, Griffin’s pixel engine (406) and pixel buffers (408) were identified as the claimed source/destination blending block and frame buffer, respectively. The method steps of claims 25-29 were argued to be taught by the combination of Griffin's processing module and memory instructions with Tarolli I's multi-texturing blending process.
    • Motivation to Combine: A POSITA would combine Tarolli I’s multi-texturing capability with Griffin’s architecture to enhance graphical image quality, a well-known goal in the industry. Tarolli I provided a known, modular solution to blend colors from multiple textures, directly addressing a limitation in Griffin’s single-texture approach and improving visual effects like specular highlights.
    • Expectation of Success: The combination was presented as a predictable application of a known technique (multi-texturing) to a known system (Griffin’s caching architecture) to achieve the expected result of more sophisticated graphical rendering.

Ground IV: Claims 10 and 11 are obvious over Griffin in view of Kilgariff.

  • Prior Art Relied Upon: Griffin (Patent 5,880,737) and Kilgariff (Patent 5,999,183).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground addressed claims reciting a "plurality of caches." Petitioner argued Griffin teaches a single tiler architecture, while Kilgariff discloses a scalable graphics subsystem with multiple rendering modules to improve performance. The proposed combination involved implementing Griffin’s tiler architecture within each of Kilgariff’s multiple rendering modules. This configuration would inherently result in a system with a "plurality of caches" and a corresponding plurality of texture address modules (one for each tiler), thereby meeting the limitations of independent claim 10. The filtering block of claim 11 would be the texture filter engine within each of the plurality of Griffin tilers.
    • Motivation to Combine: A POSITA would combine these references to create a scalable, high-performance rendering system by partitioning the workload across multiple instances of Griffin's tiler, as arranged by Kilgariff’s multi-module architecture. The motivation was strong because both references were understood to describe aspects of the same underlying Talisman architecture, suggesting inherent compatibility and a straightforward path to improving performance.
    • Expectation of Success: Combining the similar, compatible architectures of Griffin and Kilgariff to scale performance was argued to be a predictable design choice that would yield the expected benefit of higher throughput without undue experimentation.

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations including Griffin, Kilgariff, Tarolli I, and Tarolli II. These grounds argued for adding capabilities such as parallel decompression blocks (from Tarolli II) and multi-texturing (from Tarolli I) to the scalable architecture of Griffin and Kilgariff to further enhance performance and functionality.

4. Key Claim Construction Positions

  • Petitioner argued for a broad construction of the term "operably coupled," proposing it means "connected such that data or control signal information can directly or indirectly pass from one to another." This construction was asserted to be critical for the invalidity arguments, as it supported mapping the claimed "texture address module" in Griffin to a combination of physically separate but functionally connected components (texture cache control, read queue, and memory control).

5. Relief Requested

  • Petitioner requests institution of inter partes review and cancellation of claims 1-6, 10-14, and 25-29 of the ’428 patent as unpatentable.