PTAB

IPR2016-01312

Qualcomm Inc v. DSS Technology Management Inc

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1. Case Identification

2. Patent Overview

  • Title: Method of Forming a Local Interconnect in a Semiconductor Structure
  • Brief Description: The ’924 patent discloses a method for manufacturing transistors that purports to simplify the formation of local interconnects. The alleged invention replaces a known two-plug "strapping" structure with a single electrically conducting plug that directly connects a transistor's gate to a nearby diffusion region (source or drain).

3. Grounds for Unpatentability

Ground 1: Claims 7-9, 15, and 17 are anticipated by Sakamoto

  • Prior Art Relied Upon: Sakamoto (Patent 5,475,240).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sakamoto discloses every element of the challenged claims. Independent claim 7 recites a method of forming a local interconnect by depositing a conducting material in a via that exposes and contacts a gate, a sidewall spacer, and a diffusion region. Petitioner asserted that Sakamoto’s Figure 1 and its description of manufacturing steps teach this exact method, disclosing a single conducting plug (plug layer 15) in a via (opening 16) that connects a gate electrode (6) to a source/drain region (7). Sakamoto was also alleged to teach the required sidewall spacer (9'), the gate being juxtaposed to but not directly contacting the diffusion region, and the via being formed in an insulating material (interlevel insulating layer 9).
    • For the dependent claims, Petitioner argued Sakamoto discloses an n+ source/drain region (claim 8), an insulating layer made of BoroPhospho Silicate Glass (BPSG), which is a known type of silicon oxide (claim 9), and a gate electrode formed of polycrystalline silicon (claims 15 and 17).

Ground 2: Claims 10-12 are obvious over Sakamoto in view of Cederbaum

  • Prior Art Relied Upon: Sakamoto (Patent 5,475,240) and Cederbaum (Patent 5,100,817).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner established that Sakamoto teaches all limitations of the base method of claim 7 but uses a polycrystalline silicon plug. Dependent claims 10-12 further require the conducting plug to be a "metal plug," a "refractory metal plug," and formed from materials including titanium and tungsten. Petitioner argued that Cederbaum explicitly teaches using a "contact stud" made of tungsten—a refractory metal—to form an identical single-plug interconnect between a gate and a diffusion region. Cederbaum’s disclosure of a tungsten plug directly meets the material limitations of claims 10-12.
    • Motivation to Combine: A POSITA would combine Sakamoto and Cederbaum because both references address the identical problem of improving transistor interconnects in SRAM memory cells and disclose nearly identical physical structures. Cederbaum teaches that its tungsten plug offers superior conductivity and lower resistivity compared to polysilicon plugs like the one in Sakamoto. Therefore, a POSITA would have been motivated to replace Sakamoto’s polysilicon plug with Cederbaum’s known, higher-performance metal plug to achieve a predictable improvement in device performance.
    • Expectation of Success: A POSITA would have a high expectation of success, as the combination involves substituting one known conductive plug material for another within an otherwise identical, well-understood semiconductor structure to achieve the known benefits of the substituted material.

4. Key Claim Construction Positions

  • "diffusion region in a silicon substrate": Petitioner proposed this term be construed to mean "a conductive terminal region, such as a source or drain, that contains dopants implanted in the silicon substrate." Petitioner argued this construction is required by the patent’s specification, which repeatedly describes forming the diffusion regions via an ion implantation process. This construction was central because it established a clear technical definition for what the prior art must disclose. Petitioner noted that the Patent Owner agreed on the "conductive terminal region" aspect in co-pending litigation, with the primary dispute being whether the claim requires "dopants implanted in the silicon substrate."

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 7-12, 15, and 17 of the ’924 patent as unpatentable.