PTAB

IPR2016-01401

Intel Corp v. Future Link Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Performance Based Packet Ordering In A PCI Express Bus
  • Brief Description: The ’680 patent describes a two-step method for managing packet-based communications in systems like those using the PCI Express bus. The method first orders data packets according to a protocol's compliance rules and then re-orders them based on performance criteria to achieve desirable performance while maintaining protocol compliance.

3. Grounds for Unpatentability

Ground 1: Anticipation by Guthrie - Claims 1 and 7 are anticipated by Guthrie under 35 U.S.C. §102.

  • Prior Art Relied Upon: Guthrie (Patent 6,327,636).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Guthrie discloses every element of independent claims 1 and 7. Guthrie teaches an "improved information transfer methodology" for PCI systems that mirrors the ’680 patent's two-step ordering. First, Guthrie discloses generating a protocol-based order by implementing "ordering rules for PCI data transfer transaction requests ... set forth in the PCI specification." Second, Guthrie discloses generating a performance-based order by adding "new ordering rules" to "maximize performance" and "insure ... system optimization." This second step modifies the initial protocol-based order, thus anticipating the core invention. For dependent claim 7, Guthrie was alleged to teach identifying incoming channels (PCI vs. PRT requests) and then selecting from them for performance reasons.

Ground 2: Obviousness over Guthrie and Budruk - Claims 2 and 8-14 are obvious over Guthrie in view of Budruk under 35 U.S.C. §103.

  • Prior Art Relied Upon: Guthrie (Patent 6,327,636) and Budruk (a 2003 reference book, PCI Express System Architecture).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addresses the dependent claims requiring a "first arbiter" and a "second separate arbiter" to perform the two-step ordering process. Petitioner asserted that while Guthrie teaches the two-step ordering method and discloses that its ordering table sets priorities "in the form of arbitration rules," it does not explicitly detail the arbiter structure. Budruk, a standard reference on PCI Express architecture, remedies this by teaching a well-known two-level arbiter implementation: a "port arbitration" mechanism (first arbiter) followed by a "VC [virtual channel] arbitration" mechanism (second arbiter).
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would have been motivated to combine the references for several reasons. First, Guthrie expressly encouraged implementing its method using "arbitration rules," and Budruk provided a known, detailed implementation for such rules in a related, backwards-compatible technology (PCI Express). Second, the references share common design goals: Guthrie aims to "improve performance and avoid deadlocks," and Budruk's two-level arbiter framework is disclosed to provide high performance and avoid deadlock conditions. A POSITA would logically look to the contemporary PCI Express standard (Budruk) to implement an improvement for the older PCI standard (Guthrie).
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because PCI Express is a backwards-compatible evolution of PCI, and implementing Guthrie’s arbitration rules with Budruk’s known arbiter structures would be a straightforward application of known components to achieve a predictable result.

Ground 3: Anticipation by Kelley - Claims 1 and 7 are anticipated by Kelley under §102.

  • Prior Art Relied Upon: Kelley (Patent 6,760,793).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner contended that Kelley, like Guthrie, discloses the claimed two-step ordering method for PCI Express systems. For the first step (protocol-based ordering), Kelley begins with the "set of transaction ordering rules" provided by the PCI and PCIX specifications. For the second step (performance-based ordering), Kelley discloses an invention that "defines means to significantly improve the transaction ordering requirements ... for Express ... with higher performance, and while avoiding congestion and deadlock." This is achieved via "improved table entries" that modify the protocol's default ordering rules, directly mapping to the limitations of claim 1. Kelley was also alleged to teach claim 7's limitations by identifying incoming channels based on traffic class or virtual channel and then selecting from them via "internal arbitration" to improve performance.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 2 and 8-14 are obvious over Kelley in view of Budruk, and that all challenged claims (1-2 and 7-14) are either anticipated by or obvious over Budruk alone. These grounds relied on similar arguments, mapping Budruk's disclosure of protocol-based "strong ordering rules" and performance-enhancing "weak ordering rules" to the two-step method, and its explicit teaching of port and virtual channel arbiters to the arbiter limitations.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-2 and 7-14 of Patent 7,917,680 as unpatentable.