Intel Corp v. Flamm Daniel

1. Case Identification

• Case #: IPR2017-00282
• Patent #: RE40,264 E
• Filed: December 2, 2016
• Petitioner(s): Intel Corporation, GlobalFoundries US., Inc., and Micron Technology, Inc.
• Patent Owner(s): Daniel L. Flamm
• Challenged Claims: 56-63 and 70-71

2. Patent Overview

• Title: Multi-Temperature Processing
• Brief Description: The ’264 patent describes a method and system for processing a semiconductor substrate, such as a wafer, within a single chamber at two or more different temperatures. The process involves using a control circuit and temperature sensors to change and maintain substrate temperatures for pre-selected time intervals during etching.

3. Grounds for Unpatentability

Ground 1: Claims 56 and 58 are obvious over Kadomura and Matsumura

• Prior Art Relied Upon: Kadomura (Patent 6,063,710) and Matsumura (Patent 5,151,871).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Kadomura taught the core elements of independent claim 56, including a multi-temperature, two-step etching process for a stack of silicon-containing layers on a substrate holder. Kadomura disclosed a control device with a PID controller to change wafer temperature by adjusting the substrate holder temperature, including etching at temperatures above 49°C. To the extent Kadomura did not expressly teach sensing the substrate holder temperature (it taught sensing wafer temperature), Matsumura explicitly disclosed a temperature sensor embedded within a substrate holder. The combination of Kadomura and Matsumura therefore rendered claim 56 obvious. For dependent claim 58, Petitioner asserted that Kadomura’s etching examples all used a chlorine-containing gas, directly teaching this limitation.
  • Motivation to Combine: A POSITA would combine Matsumura’s substrate holder temperature sensor with Kadomura’s system to improve process control and efficiency. Kadomura controlled wafer temperature by adjusting holder temperature, making direct measurement of the holder’s temperature a logical step for process optimization. This would allow a chipmaker to better understand heat transfer dynamics between the holder and wafer, adjust recipes for faster temperature changes, and increase throughput, which was a known goal in the art.
  • Expectation of Success: Given that both references operated in the same technical field of semiconductor processing and addressed temperature control, a POSITA would have had a high expectation of success in integrating a standard component like a holder temperature sensor (from Matsumura) into a system like Kadomura’s.

Ground 2: Claim 57 is obvious over Kadomura, Matsumura, and Muller

• Prior Art Relied Upon: Kadomura (Patent 6,063,710), Matsumura (Patent 5,151,871), and Muller (Patent 5,605,600).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on the combination of Kadomura and Matsumura for claim 56 and adds Muller to teach the limitation of claim 57: changing temperature in "less than about 5 percent of the total etching process time." Petitioner argued that Muller disclosed a two-step etching process with a total time of 430 seconds, where the temperature change of 50°C occurred within "several seconds." Even if "several seconds" was interpreted as 10 seconds, this is approximately 2% of the total etch time, satisfying the claim limitation.
  • Motivation to Combine: A POSITA would incorporate Muller's rapid, continuous etch and backpressure temperature control design into the Kadomura-Matsumura system to achieve faster temperature changes and increase throughput. Kadomura and Muller relate to the same field, and Muller’s known recipe with a rapid temperature change relative to total etch time provided an established template. A POSITA would be motivated to adopt this known time ratio to optimize the process in the combined Kadomura-Matsumura system for efficiency.
  • Expectation of Success: The combination involved applying a known process parameter (the ratio of temperature-change time to total-etch time) from Muller to the analogous multi-step etching process of the primary combination. This was presented as a routine optimization with a predictable outcome.

Ground 3: Claims 56-62 and 71 are obvious over Muller, Matsumura, and Wang

• Prior Art Relied Upon: Muller (Patent 5,605,600), Matsumura (Patent 5,151,871), and Wang (Patent 4,992,391).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued this combination, with Muller as the primary reference, rendered the claims obvious. Muller taught a multi-temperature etch process for shaping profiles in layers on a wafer. As in Ground 1, Matsumura was added to provide the explicit teaching of sensing substrate holder temperature and using predetermined recipes for precise control over process times and temperatures. For claims reciting specific layer stacks (e.g., polysilicon over silicide), Wang was introduced. Wang taught etching a wafer with this specific stack configuration, including oxide layers that could serve as etch-stops. The combination of Muller’s process, Matsumura’s control system, and Wang’s specific wafer structure was argued to teach all limitations of claims like 59 and 60.
  • Motivation to Combine: A POSITA would combine Matsumura’s superior control system with Muller’s process to improve precision and repeatability, as Muller’s system showed temperature fluctuations over time. It would have been a simple design choice to apply this improved process to a known wafer structure like that in Wang. The references shared overlapping teachings in plasma etching of silicon-containing layers, providing a strong basis for combination to achieve a more robust and versatile manufacturing process.
  • Expectation of Success: Combining a more advanced control system (Matsumura) with a known process (Muller) and applying it to a standard material stack (Wang) were all conventional steps in process development. A POSITA would expect these elements to work together predictably.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations including Kikuchi (Patent 5,226,056), primarily for its teachings on using radiation (infrared lamps) for rapid heating, to challenge claims 63 and 70.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 56-63 and 70-71 of Patent RE40,264 E as unpatentable.