NVIDIA Corp v. Polaris Innovations Ltd

1. Case Identification

• Case #: IPR2017-00382
• Patent #: 7,124,325
• Filed: December 19, 2016
• Petitioner(s): NVIDIA Corporation
• Patent Owner(s): Polaris Innovations Ltd.
• Challenged Claims: 1-20

2. Patent Overview

• Title: Method And Apparatus for Internally Trimming Output Drivers and Terminations in Semiconductor Devices
• Brief Description: The ’325 patent describes a method and device for trimming semiconductor interface devices, such as output drivers. The invention purports to solve prior art issues by integrating a "trimming unit" within the semiconductor device itself to adjust parameters like impedance, thereby allowing for higher data transmission rates.

3. Grounds for Unpatentability

Ground 1: Claims 1-20 are obvious over Tanaka in view of Ikehashi

• Prior Art Relied Upon: Tanaka (Patent 7,000,160) and Ikehashi (Patent 6,643,180).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that both Tanaka and Ikehashi disclose techniques for trimming semiconductor interface devices using similar methods. Tanaka was asserted to teach a semiconductor device (claim 14) with an interface device having a settable control element (a voltage dividing circuit), a trimming register connected to it, and an internal trimming unit. This trimming unit, comprising a comparison circuit and a CPU program, writes to the trimming register based on a measured voltage (Vpp) detected on the interface device. The trimming process iteratively adjusts the control element until the measured voltage matches a nominal reference voltage (Vref). Ikehashi was argued to disclose a similar system for trimming read voltage, including an interface device with a settable variable resistor, a trimming data register, and a trimming unit that compares a measured voltage (VMON) to a reference voltage to update the register.
  • Motivation to Combine: A POSITA would combine these references to apply known solutions to improve a similar system. Petitioner asserted that Ikehashi offered a simpler, more direct feedback mechanism that eliminates the need for bus reads contemplated by Tanaka, thereby simplifying the design. Additionally, incorporating Ikehashi’s output terminal monitoring would enable improved monitoring during testing.
  • Expectation of Success: Because both references use the same general algorithm for arriving at a trimming value—comparing a measured voltage to a nominal voltage—a POSITA would have a high expectation of success in combining their features to improve Tanaka's system while staying true to its general approach.

Ground 2: Claims 1, 8-14, and 16-17 are obvious over Garrett in view of Hassoun

• Prior Art Relied Upon: Garrett (Patent 6,556,052) and Hassoun (Patent 5,844,913).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Garrett discloses the core elements of the challenged claims, including a semiconductor device with multiple interface devices (output drivers) having a settable control element (multiple current sources controlled by signals). Garrett further taught a trimming register ("CCR") and a trimming unit that compares a measured voltage (a weighed average of output high and low voltages) with a nominal reference voltage. The trimming unit then increments or decrements a counter to adjust the control signals until an equilibrium value is reached and stored in the trimming register. Hassoun was asserted to teach a test apparatus that uses a reference current source, rather than a voltage source, for testing semiconductor devices.
  • Motivation to Combine: A POSITA would combine the references to gain the benefits disclosed by Hassoun. Petitioner argued that integrating Hassoun's reference current source into Garrett’s test apparatus would create a more robust system capable of testing devices under a wider variety of conditions. This integration would have been straightforward based on the well-known relationship between voltage, current, and resistance.
  • Expectation of Success: A POSITA would expect success in the combination because both references disclose circuits in test devices for the similar purpose of providing a reference signal for testing and trimming.

Ground 3: Claims 2-7, 15, and 18-20 are obvious over Garrett in view of Hassoun and Ishikawa

• Prior Art Relied Upon: Garrett (Patent 6,556,052), Hassoun (Patent 5,844,913), and Ishikawa (Patent 5,991,221).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds upon the combination of Garrett and Hassoun from Ground 2. Petitioner asserted that Ishikawa adds the teaching of storing the determined "voltage trimming information" in a nonvolatile manner, such as in a dedicated region of flash memory. Ishikawa further teaches that upon device startup or reset, this stored trimming information is automatically read from the nonvolatile memory and loaded into the trimming registers to control the interface device.
  • Motivation to Combine: A POSITA would be motivated to add Ishikawa's teachings to the Garrett/Hassoun system to achieve the well-known design goal of preserving trimming values through power cycles. Saving the trimming value to nonvolatile memory allows the system to use the optimal value immediately upon startup without needing to re-run the trimming process, resulting in a more robust and efficient device.
  • Expectation of Success: A POSITA would have a clear expectation of success, as this combination involves adding a conventional and well-understood data storage-and-retrieval feature to an existing trimming circuit to enhance its functionality.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’325 patent as unpatentable.