PTAB

IPR2017-00382

NVIDIA Corporation v. Polaris Innovations Limited

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1. Case Identification

2. Patent Overview

  • Title: Method And Apparatus for Internally Trimming Output Drivers and Terminations in Semiconductor Devices
  • Brief Description: The ’325 patent discloses a method and apparatus for trimming semiconductor interface devices, such as output drivers and terminations, to adjust for parameter variations caused by manufacturing processes or operating conditions like temperature. The purported innovation is integrating a "trimming unit" directly within the semiconductor device itself to perform this calibration, rather than relying on an external test apparatus.

3. Grounds for Unpatentability

Ground 1: Obviousness over Tanaka and Ikehashi - Claims 1-20 are obvious over Tanaka in view of Ikehashi under 35 U.S.C. §103.

  • Prior Art Relied Upon: Tanaka (Patent 7,000,160) and Ikehashi (Patent 6,643,180).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Tanaka discloses a complete semiconductor trimming system, including an interface device with a settable control element (a boosting circuit with a variable resistor), a trimming register, and a trimming unit (a voltage trimming circuit with a comparator) that iteratively adjusts a voltage to a target value. Petitioner asserted that Ikehashi similarly discloses a system for trimming internal voltages in a semiconductor device, also using a trimming unit with a comparator to adjust a value in a trimming register. The combination was argued to teach every limitation of the challenged claims.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the references for two primary reasons. First, a POSITA would be motivated to modify Tanaka’s system with Ikehashi's teachings to implement a known solution—a simpler, more direct feedback mechanism—to improve a similar system. Second, a POSITA would integrate Ikehashi's teachings to gain additional benefits, such as improved output terminal monitoring during testing, a recognized benefit in the field.
    • Expectation of Success: Petitioner contended that because both references use the same general algorithm for trimming (comparing a measured voltage to a nominal voltage to arrive at a trimming value), a POSITA would have had a reasonable expectation of success in combining their features to improve Tanaka's system.

Ground 2: Obviousness over Garrett and Hassoun - Claims 1, 8-14, and 16-17 are obvious over Garrett in view of Hassoun under §103.

  • Prior Art Relied Upon: Garrett (Patent 6,556,052) and Hassoun (Patent 5,844,913).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Garrett teaches a semiconductor device with multiple interface devices (output drivers) having a settable control element (current sources controlled by signal ictrl[n:0]), a trimming register (CCR), and a trimming unit (a comparator and up/down counter). Garrett's system calibrates the output drivers by comparing a measured voltage against a reference voltage supplied by an external test apparatus. Hassoun was cited for its disclosure of a test apparatus that uses a variable current source to provide test signals, which Hassoun credits with enabling more robust testing under a variety of conditions.
    • Motivation to Combine: A POSITA, reviewing Garrett's system that relies on a reference voltage, would be motivated to integrate Hassoun's reference current source into Garrett's test apparatus. This modification would be driven by the recognized benefits disclosed in Hassoun for achieving more robust and versatile testing. Petitioner argued this would be an obvious design choice, given the well-understood relationship between voltage, current, and resistance in test circuits.
    • Expectation of Success: A POSITA would have reasonably expected success in combining the systems because both references disclose circuits in test devices designed for the similar purpose of providing references for testing and trimming semiconductor devices.

Ground 3: Obviousness over Garrett, Hassoun, and Ishikawa - Claims 2-7, 15, and 18-20 are obvious over Garrett in view of Hassoun and Ishikawa under §103.

  • Prior Art Relied Upon: Garrett (Patent 6,556,052), Hassoun (Patent 5,844,913), and Ishikawa (Patent 5,991,221).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the combination of Garrett and Hassoun from Ground 2 and adds the teachings of Ishikawa. While Garrett/Hassoun provides the core trimming system, Petitioner argued that Ishikawa adds the explicit teaching of storing the determined "voltage trimming information" in a nonvolatile manner, such as in a dedicated region of a flash memory array. This mapping addresses dependent claims requiring the storage of trimming values in nonvolatile memory for later use.
    • Motivation to Combine: A POSITA would be motivated to add Ishikawa's teachings to the Garrett/Hassoun combination to improve the system's robustness. Saving the trimming value to nonvolatile memory allows the calibrated setting to be retained and used after a system reset or power loss, eliminating the need for re-trimming on every startup. This was presented as a long-standing and well-known design goal in the art to improve efficiency and reliability.
    • Expectation of Success: The combination was asserted to be predictable, as implementing nonvolatile storage for configuration data (like trimming values) was a common and well-understood practice for preserving system states through power cycles.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued for institution of all grounds by asserting they are not redundant. It was argued that Ground 1 is distinct from Grounds 2 and 3 because it presents prior art under §102(e), which is subject to different potential antedating challenges than the §102(b) art presented in the other grounds.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’325 patent as unpatentable.