Apple Inc v. California Institute Of Technology

1. Case Identification

• Case #: IPR2017-00703
• Patent #: 8,284,833
• Filed: February 16, 2017
• Petitioner(s): Apple Inc.
• Patent Owner(s): California Institute of Technology
• Challenged Claims: 1-14

2. Patent Overview

• Title: Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes
• Brief Description: The ’833 patent discloses an apparatus and method for encoding data using irregular repeat-accumulate (IRA) codes. The technology involves repeating information bits an irregular number of times, permuting (reordering) the repeated bits, and accumulating them to generate parity bits for error correction in data transmission.

3. Grounds for Unpatentability

Ground 1: Claims 1-14 are obvious over the '710 Patent in view of MacKinnon.

• Prior Art Relied Upon: Patent 7,116,710 (“’710 patent”) and Duncan MacKinnon, “Preliminary Software Development For Optical Mirror Figure Control” (a 1971 publication, “MacKinnon”).
• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner’s argument centered on first establishing the ’710 patent as prior art and then combining its teachings with MacKinnon. Petitioner asserted that the ’833 patent is not entitled to its claimed priority date because its priority documents describe only an abstract encoding algorithm, failing to provide written description support for the specific computer and memory-based implementation recited in the claims. This lack of support, Petitioner argued, gives the ’833 patent an effective filing date of March 28, 2011, making the ’710 patent—which issued in 2006 and has a nearly identical specification—valid prior art under 35 U.S.C. §102.

  • Petitioner argued that the ’710 patent teaches all the fundamental error-correcting code aspects of the challenged claims, including an IRA encoder comprising a repeater, a permuter, a summer, and an accumulator. However, it describes these elements at a high, algorithmic level. MacKinnon, published decades earlier, teaches the routine and well-understood task of implementing matrix multiplication on a digital computer, including storing matrices and vectors in memory arrays and using nested loops for computation.

  • The petition contended it was obvious to a Person of Ordinary Skill in the Art (POSITA) to implement the ’710 patent’s distinct repeat, permute, and sum steps as a single, consolidated matrix-vector multiplication, a standard technique in linear algebra. Applying MacKinnon’s established computer implementation method to this consolidated matrix operation would directly result in the apparatus of claim 1. Specifically, the matrix multiplication process itself would function as the claimed “permutation module.” This module would “read a bit from the first set of memory locations” (i.e., from the input vector stored in memory, analogous to vector B in MacKinnon) and “combine” it with a bit in the “second set of memory locations” (the output vector, R in MacKinnon) via the multiplication and addition steps inherent to the algorithm. The combination would be “based on a corresponding index” of the memory locations, as determined by the row and column indices of the consolidated matrix. Further, the claim limitation requiring that memory locations be read a "different number of times" would be met because the number of non-zero entries in each column of the consolidated matrix dictates how many times each corresponding input bit is read, and this can be irregular by design. The final accumulation step taught by the ’710 patent would then be performed on the results stored in the second set of memory locations.

  • Motivation to Combine: A POSITA would combine the ’710 patent’s IRA encoding algorithm with the computer implementation techniques taught by MacKinnon to create a practical, efficient system. The primary motivation would be computational efficiency. Consolidating the three separate encoding steps (repeat, permute, sum) into a single matrix multiplication would drastically reduce the total number of required memory operations and computer instructions, leading to a significantly faster encoder. Petitioner provided an example showing this consolidation could reduce memory operations from 216 to just 24.

  • Expectation of Success: A POSITA would have a high expectation of success. Implementing well-defined linear algebra operations like matrix-vector multiplication on a computer was a routine and thoroughly understood task at the time, as evidenced by MacKinnon and other similar references from the 1970s.

4. Key Claim Construction Positions

• "combine": Petitioner proposed this term be construed as "perform logical operations on," noting this construction was previously adopted in related district court litigation.
• "permutation module": Proposed construction was "a module that changes the order of data elements." This construction is critical to Petitioner’s argument that the entire consolidated matrix multiplication process functions as the claimed module, rather than just a simple interleaver.
• "wherein two or more memory locations... are read... different times from one another": Proposed construction was "read a different number of times from one another." Petitioner argued this clarifies that the claim requires an irregular number of read operations on the input bits, a key feature of the allegedly obvious implementation.

5. Key Technical Contentions (Beyond Claim Construction)

• Priority Date Challenge: The petition’s foundational technical argument was that the ’833 patent is not entitled to the priority date of its parent applications. Petitioner contended that the priority documents failed to demonstrate that the inventors were in possession of the specific claimed invention—an apparatus with memory sets and a permutation module that reads and combines bits in a particular manner. Because this specific computer implementation was allegedly first disclosed in the ’833 patent application itself, Petitioner argued its effective filing date is in 2011, which crucially renders the ’710 patent prior art.

6. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-14 of Patent 8,284,833 as unpatentable.