Apple Inc. v. California Institute of Technology

1. Case Identification

• Case #: IPR2017-00703
• Patent #: 8,284,833
• Petitioner(s): Apple Inc.
• Patent Owner(s): California Institute of Technology
• Challenged Claims: 1-14

2. Patent Overview

• Title: Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes
• Brief Description: The ’833 patent describes an apparatus and method for performing encoding operations using irregular repeat-accumulate (IRA) codes. The invention focuses on a specific computer-based implementation involving memory locations, permutation modules, and accumulators to process information bits into parity bits for error correction.

3. Grounds for Unpatentability

Ground 1: Claims 1-14 are obvious over the '710 patent in view of MacKinnon.

• Prior Art Relied Upon: Patent 7,116,710 (“’710 patent”) and Duncan MacKinnon, “Preliminary Software Development For Optical Mirror Figure Control,” (a 1971 publication, hereinafter “MacKinnon”).

• Core Argument for this Ground: Petitioner’s central argument was twofold. First, it contended that the ’833 patent was not entitled to its claimed priority date (going back to applications filed in 2000). Petitioner argued the challenged claims, filed in 2011, introduced new matter by reciting a specific computer implementation (e.g., reading bits from memory locations) that was not described in the priority documents. This alleged lack of written description support makes the ’710 patent—one of the parent patents—prior art under §102(b) because it was issued in 2006, more than a year before the ’833 patent’s effective filing date.

  Second, with the ’710 patent established as prior art, Petitioner argued that the challenged claims were obvious. The ’710 patent was asserted to teach all the error-correcting code aspects of the invention (the IRA encoder). MacKinnon, a 1971 publication, was asserted to teach the implementation of linear algebra operations (specifically matrix multiplication) on a computer using memory arrays. Petitioner argued that combining the abstract IRA code from the ’710 patent with the well-known computer implementation techniques taught by MacKinnon would have been obvious to a person of ordinary skill in the art (POSITA).

  • Prior Art Mapping: Petitioner mapped the claims by asserting that the ’710 patent discloses the fundamental structure of the claimed IRA encoder, including a repeater, a permuter (interleaver), a summer, and an accumulator. The novel elements of the ’833 patent claims were argued to be merely the implementation of these functions on a computer with memory. Petitioner explained that the repeat, permute, and sum operations of the ’710 patent's encoder could be represented as a series of matrix-vector multiplications, which could be consolidated into a single matrix-vector multiplication.

    MacKinnon was argued to teach exactly how to implement such matrix-vector multiplications on a computer. MacKinnon described storing matrices as arrays in memory, using indices to access specific elements, and performing the necessary read, multiply, and add operations to compute the result. Therefore, implementing the consolidated matrix from the ’710 patent using MacKinnon's method would result in reading bits from a first set of memory locations (the input vector), combining them with bits in a second set of memory locations (the output vector), and storing the result—thereby meeting the key limitations of independent claims 1 and 8. The limitation in claim 1 requiring that memory locations are read a "different number of times" was allegedly met because in the consolidated matrix, the number of "1s" in each column (dictating how many times an input bit is read) would be different, reflecting the irregular nature of the code.

  • Motivation to Combine: A POSITA would be motivated to implement the error-correcting code taught by the ’710 patent on a computer for practical use. MacKinnon and similar references demonstrated that implementing linear algebra operations on computers was a standard, well-known practice for decades. Furthermore, Petitioner argued there was a strong motivation of efficiency. Consolidating the repeat, permute, and sum steps into a single matrix multiplication, as taught by linear algebra, and implementing it using MacKinnon’s techniques would drastically reduce the number of required memory operations and computations compared to performing each step separately, making the system faster and more efficient.

  • Expectation of Success: A POSITA would have had a high expectation of success because MacKinnon provided a detailed, working example of implementing matrix multiplication on a digital computer, and the underlying mathematical principles of error-correcting codes and linear algebra were well-established.

4. Key Claim Construction Positions

• "combine" (claims 1-7, 9, 10): Petitioner asserted this term should be construed to mean "perform logical operations on," consistent with a construction adopted in the related Hughes district court litigation. This is important for mapping the addition and multiplication steps in MacKinnon's algorithm to the claim language.
• "permutation module" (all claims): This term should be construed as "a module that changes the order of data elements." Petitioner argued that the claimed module is not a simple interleaver but a functional block that reads bits in one order and writes combinations of bits, effectively changing the data element order as required by the claim.
• "wherein two or more memory locations... are read... different times" (claim 1): Petitioner proposed this should be construed to mean "wherein two or more memory locations of the first set of memory locations are read a different number of times from one another." This construction clarifies that "different times" refers to frequency, which Petitioner argued is a direct result of implementing the irregular code structure as a consolidated matrix.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-14 of Patent 8,284,833 as unpatentable.