PTAB

IPR2017-00814

Amazon.com Inc v. Broadcom Corp

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System on a Chip for Networking
  • Brief Description: The ’389 patent describes a system-on-a-chip (SoC) for networking devices. The invention integrates multiple components onto a single integrated circuit, including at least one processor, a cache memory, a memory controller, a bridge circuit, and network interface circuits, all coupled to a common bus or interconnect.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-5, 7, 9, and 13 under 35 U.S.C. §102 by Shigeeda

  • Prior Art Relied Upon: Shigeeda (Patent 5,778,425).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Shigeeda disclosed every element of the challenged independent claims. Shigeeda’s microprocessor unit (MPU) and peripheral processor unit (PPU), which it teaches can be integrated into a single chip, collectively form the claimed integrated circuit. This SoC includes a processor (CPU core 702), cache memory (cache 704), memory controller (718), and a bridge circuit (bus bridge 716), all coupled to an internal bus (bus 714). Petitioner contended that Shigeeda’s peripheral unit also contains interface circuits (e.g., XD/IDE interface 934, IR serial port 935) coupled to the bridge circuit for connection to external networks, and that the bridge is disclosed as initiating transactions on the bus for data transfer.
    • Key Aspects: For dependent claims, Petitioner asserted Shigeeda also disclosed the bridge operating to maintain cache coherency (claim 4) and the inclusion of multiple interface circuits coupled to the bridge (claim 5).

Ground 2: Obviousness of Claims 5-7, 9-11, and 13 over Shigeeda in view of Givargis

  • Prior Art Relied Upon: Shigeeda (Patent 5,778,425) and Givargis ("Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design," 2000).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground focused on claims requiring multiple interface circuits for multiple networks. Petitioner argued that Shigeeda provided the fundamental SoC architecture, as described in Ground 1. Givargis was introduced as teaching a parameterized SoC design for networking applications that explicitly includes a bridge connecting a system bus to multiple "peripheral cores," which include network interfaces. The combination, Petitioner asserted, rendered claims requiring multiple network interfaces obvious.
    • Motivation to Combine: A POSITA would combine Givargis’s teaching of multiple peripheral network interfaces with Shigeeda’s base SoC architecture to achieve the well-known benefits of system integration. These benefits included reduced board space, lower power consumption, and improved performance, all of which were significant design goals for SoCs at the time.
    • Expectation of Success: Petitioner argued success would be predictable, as the combination involved integrating known types of I/O circuits (network interfaces) onto an established SoC architecture using conventional design principles.

Ground 3: Obviousness of Claims 14-18 over Shigeeda and Givargis, in further view of Young

  • Prior Art Relied Upon: Shigeeda (Patent 5,778,425), Givargis (conference proceeding), and Young (Patent 5,768,548).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground challenged claims 14-18, which added specific limitations regarding the bridge circuit's functionality in maintaining cache coherency (e.g., coherently reading a cache block, modifying it within the bridge, and writing it back). Petitioner argued that while Shigeeda and Givargis disclosed the base SoC with a bridge, Young taught a sophisticated bus bridge specifically designed to solve coherency problems between a peripheral bus and a memory bus. Young’s bridge uses internal data buffers to receive write commands, temporarily store and modify data within the bridge itself, and coherently manage write-back operations to memory.
    • Motivation to Combine: A POSITA would have been motivated to replace or enhance the bridge in the Shigeeda/Givargis system with the more advanced bridge taught by Young. The motivation was to address the known and critical issue of cache coherency in shared memory systems, thereby improving system stability and performance. Young's bridge directly addressed the performance bottlenecks and data integrity issues that arise when slower I/O devices interact with a high-speed processor/memory subsystem.
    • Expectation of Success: The expectation of success was high because modifying an SoC design to incorporate a more capable bus bridge was a standard engineering approach to improving performance and ensuring data coherency.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claims 8, 12, and 19 based on the combination of the above references with an HT Press Release describing "Lightning Data Transport" (HyperTransport) technology as a high-performance point-to-point interface.

4. Key Claim Construction Positions

  • "Level 2 cache" (Claim 3): Petitioner proposed this term should be construed to mean “a cache that is external to a microprocessor core, but on the same integrated circuit package.” Petitioner argued this construction was consistent with the ’389 patent’s disclosure, which distinguishes the L2 cache from the L1 cache internal to a processor. This construction supports the argument that the cache disclosed in Shigeeda, which is on-chip but external to the CPU core, meets the claim limitation.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-19 of the ’389 patent as unpatentable.