NVIDIA Corp v. Polaris Innovations Ltd

1. Case Identification

• Case #: IPR2017-00901
• Patent #: 7,405,993
• Filed: February 14, 2017
• Petitioner(s): NVIDIA Corporation
• Patent Owner(s): Srdjan Djordevic
• Challenged Claims: 1-14

2. Patent Overview

• Title: Control Component for Controlling a Semiconductor Memory Component in a Semiconductor Memory Module
• Brief Description: The ’993 patent discloses a control component for semiconductor memory modules that multiplexes address signals and control signals over common terminals. This allows the component to support different memory configurations without requiring dedicated pins for every signal type.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ajanovic - Claims 1, 2, 4, 7, and 8 are obvious over Ajanovic

• Prior Art Relied Upon: Ajanovic (Patent 6,298,426)
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Ajanovic teaches a memory controller configurable for multiple memory organizations, addressing the same problem as the ’993 patent. Ajanovic’s controller core generates both address signals (MA13-0) and control signals (RAS7-0/CS7-0). Crucially, Ajanovic explicitly discloses using multiplexers as selection circuits to supply a common output pin with a selected signal. For example, multiplexer 402B receives a control signal (chip select 7-6) and a memory address signal (MA3-2) as inputs and selects one to output based on a configuration signal (CFGAB). This directly maps to the core limitation of claim 1, which requires a selection circuit that selects between an address signal and a control signal to supply an address terminal.
  • Motivation to Combine (for §103 grounds): This ground relies on a single reference. Petitioner asserted Ajanovic alone renders the claims obvious.
  • Expectation of Success (for §103 grounds): Not applicable (single reference).

Ground 2: Obviousness over LaBerge - Claims 1-10 are obvious over LaBerge

• Prior Art Relied Upon: LaBerge (Application # 2005/0177690)
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended LaBerge discloses a memory hub that handles signaling for different memory configurations (DDR2 and DDR3) by coupling different signals to the same bus lines depending on the operational mode. LaBerge’s memory controller uses "Signal Swap Multiplexers 230" to route command and address signals to the correct terminals based on a "CONFIG command." LaBerge’s Table 1 explicitly shows terminals that selectively supply either address signals or control signals; for instance, terminal D28 provides a Chip Select signal (CSZ0) in DDR2 mode and an address signal (A10) in DDR3 mode. This selection between address and control signals for a common terminal via multiplexers meets the limitations of claim 1. LaBerge further discloses control signals for on-die termination (ODT) and a module layout with a central controller flanked by memory components, mapping to various dependent claims.
  • Motivation to Combine (for §103 grounds): This ground relies on a single reference. Petitioner asserted LaBerge alone renders the claims obvious.
  • Expectation of Success (for §103 grounds): Not applicable (single reference).

Ground 3: Obviousness over Kinsley and Swanson - Claims 1, 2, 4, 7, and 8 are obvious over Kinsley in view of Swanson

• Prior Art Relied Upon: Kinsley (Application # 2006/0044860) and Swanson (Application # 2003/0046507)

• Core Argument for this Ground:

  • Prior Art Mapping: Kinsley described solving the problem of needing additional chip select signals for stacked memory configurations by using an "unused address pin" (specifically, the A15 pin) to transmit an additional chip select signal. Kinsley thus taught that the same terminal could be used to transmit either an address signal or a control signal, depending on the memory configuration's needs. However, Kinsley did not explicitly disclose the selection circuitry. Swanson was introduced to supply this missing element, as it teaches memory controllers with "pins with selectable functionality" and explicitly discloses using a multiplexer to create "dual function pins." Swanson’s multiplexer selects between different input signals (e.g., chip select and clock signals) to drive a single output pin.
  • Motivation to Combine (for §103 grounds): A POSITA, reading Kinsley's disclosure of a selectable-function pin but lacking implementation details, would combine it with Swanson's explicit teaching of using a multiplexer to achieve this exact functionality. Both references shared the goal of leveraging unused pins to increase functionality, making the combination logical to solve Kinsley's implementation problem with Swanson's known circuit solution.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success, as it would involve a simple substitution of one of Swanson's signal inputs (e.g., a clock signal) with Kinsley's address signal (A15) into a standard multiplexer circuit.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including:

  • Ground 4 (claims 9, 10, 12-14) added Hung and Holman to the Kinsley/Swanson combination to provide motivation and known layouts for locating the memory controller on the memory module itself.
  • Ground 5 (claims 1-11, 14) added Bhakta to LaBerge to provide explicit support for well-known features like "addressing memory cells" and details of on-die termination (ODT) circuits responsive to ODT signals.
  • Grounds 6 and 7 added Stave to Ajanovic and Kinsley/Swanson, respectively, to provide explicit disclosure for well-known features like memory cells and activatable terminating resistors for write access, which were otherwise implicit in the primary references.

4. Key Claim Construction Positions

• "address terminal" / "control terminal": Petitioner argued that these terms should not be limited to terminals used exclusively for address or control signals, respectively. Based on the specification and the understanding of a POSITA, Petitioner proposed they should be construed functionally as "a terminal that is capable of providing an address signal" or "a terminal that is capable of providing a control signal." This construction was central to the invalidity arguments, as the core of the prior art teachings involved terminals that served dual purposes depending on the memory configuration.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-14 of the ’993 patent as unpatentable.