PTAB
IPR2017-01183
Advanced Micro Devices Inc v. Broadcom Corp
Key Events
Petition
Table of Contents
petition Intelligence
1. Case Identification
- Case #: IPR2017-01183
- Patent #: 7,720,294
- Filed: March 28, 2017
- Petitioner(s): Advanced Micro Devices, Inc.
- Patent Owner(s): Broadcom Corporation
- Challenged Claims: 1-3, 9-11
2. Patent Overview
- Title: Unified Video Decoder
- Brief Description: The ’294 patent describes a unified video decoder designed to process video data encoded in multiple formats. The system avoids dedicated hardware for each format by using a host processor to send an indication of the encoding standard to a discrete video decoder, which then executes the corresponding set of firmware instructions to decode the video.
3. Grounds for Unpatentability
Ground 1: Obviousness over Nguyen and Wise - Claims 1, 3, 9, and 11 are obvious over Nguyen in view of Wise.
- Prior Art Relied Upon: Nguyen (Patent 6,425,054) and Wise (Patent 7,230,986).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Nguyen discloses nearly every element of the independent claims, including a firmware-based video decoder (“multimedia card 100”) with a master processor that is discrete from a host computer system’s processor. The only element Petitioner contended Nguyen does not explicitly disclose is the host processor sending a specific "indication" of the video standard to the decoder. Wise allegedly cures this deficiency by teaching a similar firmware-based, multi-standard decoder that receives a specific "indication" (a “CODING_STANDARD” token) from a microprocessor to select and execute the correct set of instructions.
- Motivation to Combine: A person of ordinary skill in the art (POSITA) would understand that Nguyen's flexible decoder would require an indication to select the correct standard. A POSITA would combine Wise’s explicit teaching of sending such an indication with Nguyen’s similar system to achieve the predictable result of a fully functional multi-standard decoder.
- Expectation of Success: Petitioner asserted that incorporating Wise’s token-based indication into Nguyen's system represented a predictable use of prior art elements according to their established functions.
Ground 2: Obviousness over Nguyen and Molloy - Claims 1-3 and 9-11 are obvious over Nguyen in view of Molloy.
- Prior Art Relied Upon: Nguyen (Patent 6,425,054) and Molloy (Patent 6,909,744).
- Core Argument for this Ground:
- Prior Art Mapping: As an alternative to Ground 1, Petitioner asserted that Molloy could also supply the "indication" element allegedly missing from Nguyen. Molloy discloses a multi-standard video decoder that is configured by a discrete host processor. The host processor provides an "indication" by loading configuration data corresponding to a selected standard into the decoder's configuration register. This act of writing to the register serves as the claimed indication.
- Motivation to Combine: Petitioner argued a POSITA seeking to implement the indication functionality in Nguyen's system would have looked to similar systems like Molloy. A POSITA would combine the two references by programming Nguyen's host processor to provide control signals that write to a register in the video decoder, as taught by Molloy.
- Expectation of Success: The combination was presented as yielding only predictable results, as it involved applying a known technique (Molloy's register-based indication) to a similar system (Nguyen's decoder) to solve a known problem.
Ground 3: Anticipation by Pearson - Claims 1-3 and 9-11 are anticipated by Pearson.
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Pearson discloses every limitation of the challenged claims in a single reference. Pearson describes a reconfigurable video codec where a discrete host processor (“CPU module 108”) provides an indication to a video decoder. This indication causes the decoder to load the appropriate program (a set of instructions) from an instruction memory (“memory module 102”) into a master processor within the decoder (“FPGA module 114”). The FPGA then executes these instructions to decode video according to the selected standard, directly mapping to the elements of independent claims 1 and 9. Pearson also explicitly discloses support for multiple standards, including MPEG-2 and MPEG-4, anticipating dependent claims 2 and 10.
Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 1A) against claims 2 and 10. This ground argued that while Nguyen and Wise teach multi-standard decoding, they predate the MPEG-4 standard. A POSITA would have been motivated to add Molloy's explicit disclosure of MPEG-4 decoding to the flexible Nguyen/Wise combination to support the newer standard.
4. Key Claim Construction Positions
- Petitioner argued for a broad construction of the phrase "wherein the video decoder executes," asserting it should mean that any component of the video decoder may execute the claimed instructions. This construction was presented as critical to prevent Patent Owner from arguing that only the specifically recited "master processor" can perform the execution. Under Petitioner's broader construction, prior art systems where a component other than the master processor (e.g., a Huffman decoder in Wise) executes instructions would still meet the claim limitation.
5. Relief Requested
- Petitioner requests institution of an inter partes review and cancellation of claims 1-3 and 9-11 of Patent 7,720,294 as unpatentable.
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