PTAB
IPR2017-01226
LG Electronics Inc v. ATI Technologies ULC
Key Events
Petition
Table of Contents
petition Intelligence
1. Case Identification
- Case #: IPR2017-01226
- Patent #: 9,582,846
- Filed: April 3, 2017
- Petitioner(s): LG Electronics, Inc.
- Patent Owner(s): ATI Technologies ULC
- Challenged Claims: 1-8
2. Patent Overview
- Title: Unified Shader
- Brief Description: The ’846 patent discloses a graphics processing architecture featuring a "unified shader" capable of performing both vertex and pixel manipulation operations. The system includes an arbiter circuit that selects between vertex and pixel data inputs to be processed by the unified shader based on a control signal.
3. Grounds for Unpatentability
Ground 1: Anticipation by Lindholm - Claims 1-4, 7, and 8 are anticipated by Lindholm under §102(e).
- Prior Art Relied Upon: Lindholm (7,038,685).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Lindholm disclosed every limitation of the challenged claims. Lindholm's "Programmable Graphics Processing Pipeline" with its "Execution Pipelines" (240) that process both vertex and pixel samples corresponded to the claimed "unified shader." The "Thread Control Unit" (420) in Lindholm was alleged to be the claimed "arbiter circuit," which selects inputs based on thread allocation and execution priorities, including resource availability. Petitioner asserted Lindholm’s "Execution Unit" (470) with its programmable computation units (PCUs) simultaneously processed different sample types (vertex and pixel) at various degrees of completion, meeting the limitations of claims 1, 4, and 7. The arbitration scheme was shown to select vertex data if resources were available, meeting claim 8's limitations.
Ground 2: Obviousness over Lindholm and Orenstien - Claims 1-8 are obvious over Lindholm, and claims 5 and 6 are obvious over Lindholm in view of Orenstien under §103.
- Prior Art Relied Upon: Lindholm (7,038,685), Orenstien (5,835,748).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that to the extent Lindholm does not explicitly disclose every limitation, the challenged claims would have been obvious from its teachings. For dependent claim 5, which recites a processor unit with logically partitioned sections for "floating point arithmetic" and "scaler operations," Petitioner argued a POSITA would have found it obvious to modify Lindholm’s programmable computation units (PCUs). Orenstien taught using dedicated floating-point units as partitioned sections in a graphics processor. Petitioner asserted that Lindholm itself taught scaler operations (in the form of vector normal calculations), or alternatively, that Orenstien taught dedicated scalar operation sections.
- Motivation to Combine (for §103 grounds): A POSITA would combine Orenstien’s floating-point and scalar units with Lindholm’s architecture to improve the efficiency and execution of graphics instructions, achieve better dynamic range than fixed-point representations, and gain greater accuracy.
- Expectation of Success (for §103 grounds): Combining known, specialized processing units like those in Orenstien into the programmable architecture of Lindholm was a predictable design choice that would have yielded expected improvements in performance.
Ground 3: Anticipation by Stuttard - Claims 1-4, 7, and 8 are anticipated by Stuttard under §102(b).
Prior Art Relied Upon: Stuttard (WO 00/62182).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Stuttard disclosed a graphics processing system that anticipated the claims. Stuttard’s "processing core 10," which processes both pixel and vertex data, was identified as the claimed "unified shader." The "thread manager 102" was mapped to the "arbiter circuit," as it provides instructions and assigns relative priorities to threads ("arbitration scheme") to direct the operation of the processing blocks. Stuttard’s system was shown to perform vertex and pixel operations simultaneously at various degrees of completion by halting, yielding, and switching between active threads to keep processing blocks busy, thus meeting the limitations of claims 1, 4, and 7. Petitioner contended that Stuttard's priority selection scheme inherently would only perform vertex operations if sufficient resources were available, anticipating claim 8.
Additional Grounds: Petitioner asserted additional obviousness challenges under Ground 4, arguing claims 1-8 are obvious over Stuttard, with claims 5 and 6 also rendered obvious by Stuttard in combination with Lindholm or Orenstien based on similar motivations to improve processor efficiency.
4. Arguments Regarding Discretionary Denial
- Petitioner argued that the Patent Owner, ATI, was collaterally estopped from re-litigating its claim to a priority date earlier than the effective filing date of the Lindholm reference. This issue was allegedly fully litigated and resolved against ATI in final written decisions for related IPRs (IPR2015-00325 and IPR2015-00326), making Lindholm qualifying prior art for the present proceeding.
5. Relief Requested
- Petitioner requests institution of an inter partes review and cancellation of claims 1-8 of the ’846 patent as unpatentable.
Analysis metadata