PTAB

IPR2017-01410

Intel Corp v. Alacritech Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Intelligent Network Interface Device and System for Accelerated Communication
  • Brief Description: The ’880 patent describes a method and system for accelerating network communications by offloading protocol processing from a host computer's CPU to an intelligent network interface card (NIC). The NIC provides a "fast-path" that processes most network messages, bypassing the host CPU to reduce its processing load and improve data transfer speeds.

3. Grounds for Unpatentability

Ground 1: Obviousness over Thia and Tanenbaum96 - Claims 32, 34, 35, 39, and 41-43 are obvious over Thia in view of Tanenbaum96.

  • Prior Art Relied Upon: Thia (a 1995 paper titled "A Reduced Operation Protocol Engine (ROPE) for a multiple-layer bypass architecture") and Tanenbaum96 (a 1996 textbook, "Computer Networks").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Thia taught the core concept of the ’880 patent: a hardware-based "bypass" system on a network interface that offloads critical, repetitive protocol functions from the host CPU to accelerate data transfer. Thia's system identifies packets eligible for this "fast path" and processes them on a dedicated "ROPE" chip, while non-eligible packets are handled by the host's standard protocol stack. However, Thia described its implementation in the context of the older OSI protocol model. Tanenbaum96, a widely-cited textbook, was alleged to supply the missing details by describing the then-dominant TCP/IP protocol, including functionally similar "fast path" processing based on header prediction. Tanenbaum96 explicitly taught that a TCP transport entity could be implemented on a network interface card and detailed standard TCP/IP operations like parsing headers, using source/destination identifiers to form a key, and looking up connection records in a hash table—all of which Petitioner mapped to limitations in independent claims 32 and 41.
    • Motivation to Combine: A POSITA would combine Thia's hardware offloading architecture with the TCP/IP protocol details from Tanenbaum96 for several reasons. By the mid-1990s, TCP/IP had become the standard for the rapidly growing internet, while OSI had "quietly vanished." A POSITA would have been motivated to adapt Thia's performance-enhancing architecture to the prevalent TCP/IP protocol to make it commercially relevant and usable for internet traffic. Furthermore, Tanenbaum96's detailed description of TCP fast-pathing and connection lookups would have been seen as a way to improve and optimize Thia's more general bypass concept.
    • Expectation of Success: Petitioner asserted a POSITA would have a high expectation of success. Thia itself stated its architecture could be used with "any standard protocol." Both OSI and TCP/IP are multi-layered protocols with functionally similar transport layers, designed to allow for modularity and protocol substitution. Given the functional similarities and the widespread availability of TCP/IP implementation code, adapting Thia's hardware offload from OSI to TCP/IP would have been a straightforward and predictable engineering task, not requiring undue experimentation.

Ground 2: Obviousness over Thia, Tanenbaum96, and Nahum - Claims 37 and 38 are obvious over Thia in view of Tanenbaum96 and Nahum.

  • Prior Art Relied Upon: Thia, Tanenbaum96, and Nahum (a 1994 paper titled "Performance Issues in Parallelized Network Protocols").
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon the combination of Thia and Tanenbaum96 from Ground 1 and adds Nahum to address the limitations of dependent claims 37 and 38. These claims add the requirement that the host computer system comprises "multiple processors for processing network packets." The combination of Thia and Tanenbaum96 teaches the offloading of fast-path processing to the NIC, leaving the host to process non-bypassed packets, but does not specify the host's processor architecture. Nahum was argued to directly supply this missing element. It explicitly taught using a host computer with multiple processors (a "shared memory multiprocessor") to perform parallel processing of TCP/IP packets to improve network throughput.
    • Motivation to Combine: The motivation was to further improve overall system performance. A POSITA seeking to build the high-performance system of Thia and Tanenbaum96 would recognize that the host system still needed to process non-bypassed packets. As network bandwidths increased, a single host CPU could become a bottleneck. Nahum addressed this exact problem by teaching the use of multiple host processors to handle TCP/IP traffic. A POSITA would have been motivated to incorporate Nahum's teaching to ensure the host system (the "slow path") could keep pace with the accelerated NIC (the "fast path"), thereby optimizing the entire communication system.
    • Expectation of Success: Petitioner argued this combination would be obvious and predictable. Thia's architecture is agnostic to the specific design of the host computer it connects to. Nahum described a now-common host architecture (multiprocessor) running the standard TCP/IP protocol. Combining a multiprocessor host (from Nahum) with a NIC-based offload engine (from Thia/Tanenbaum96) would have been a well-understood and logical design choice for building a high-throughput networking system.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 32, 34, 35, 37-39, and 41-43 of the ’880 patent as unpatentable.