Samsung Electronics Co Ltd v. ProMOS Technologies Inc

1. Case Identification

• Case #: IPR2017-01412
• Patent #: 6,069,507
• Filed: May 12, 2017
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Promos Technologies, Inc.
• Challenged Claims: 10, 11, 13, and 15

2. Patent Overview

• Title: Circuit and Method for Reducing Delay Line Length in Delay-Locked Loops
• Brief Description: The ’507 patent relates to delay-locked loops (DLLs) used for clock deskew functionality in integrated circuits. The invention purports to provide a circuit and method for reducing the physical length and number of delay elements in the DLL's delay line, thereby saving space and power.

3. Grounds for Unpatentability

Ground 1: Obviousness over Donnelly in view of Iwamoto - Claims 10 and 11

• Prior Art Relied Upon: Donnelly (Patent 5,945,862) and Iwamoto (Patent 6,292,040).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Donnelly disclosed a digital DLL that met most limitations of claim 10, including a method for reducing delay line length. Donnelly achieved this reduction by using a boundary detector that allowed the number of delay elements to be cut in half (from 64 to 32) compared to conventional designs. Petitioner asserted that Donnelly’s phase detector and delay chains taught the steps of determining a phase difference and delaying an input clock to compensate. However, Donnelly used an up/down counter to select the appropriate delay tap. Petitioner contended that Iwamoto, which addressed the same field of DLLs, disclosed a functionally equivalent shift register for selecting delay taps based on phase comparison.
  • Motivation to Combine: A POSITA would have been motivated to modify Donnelly’s DLL by replacing its up/down counter with Iwamoto’s well-known shift register. Petitioner argued this was a simple substitution of one known element for another to obtain predictable results, as Donnelly provided the high-level functionality but lacked specific implementation details for its counter, for which a POSITA would consult a reference like Iwamoto.
  • Expectation of Success: Given that shift registers were commonly used in DLLs for the exact purpose disclosed in Iwamoto, a POSITA would have had a reasonable expectation of success in integrating Iwamoto's shift register into Donnelly’s circuit to achieve the claimed functionality.
  • Key Aspects: For dependent claim 11, Petitioner argued that Donnelly's phase detector inherently possessed a "first resolution" because any functional phase detector must be able to distinguish between phases to some degree of precision.

Ground 2: Anticipation by Jefferson - Claims 13 and 15

• Prior Art Relied Upon: Jefferson (Patent 5,744,991).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Jefferson, which discloses a digital DLL, anticipated all limitations of claim 13. The core of the argument centered on Jefferson’s macro phase detector circuit (Fig. 3A). Petitioner asserted this circuit performed the claimed step of "determining whether a feedback clock signal... follows within a 180° phase difference." Specifically, Jefferson's D flip-flop (FF2) samples the feedback clock on the rising edge of a reference clock; its resulting low or high output state directly corresponds to whether the feedback clock lags by less than or more than 180°.
  • Prior Art Mapping (cont.): This output from the flip-flop then served as a control input to combinational logic (disclosed as an XOR gate), which performed the claimed step of "selecting a switch position." When the flip-flop output was low (indicating the feedback clock was within 180°), the XOR gate selected a first output state ("first switch position"). For dependent claim 15, when the flip-flop output was high (indicating the feedback clock was not within 180°), the XOR gate selected its alternate, inverted output state ("second switch position"), thereby meeting the claim's additional limitation.

4. Key Claim Construction Positions

• Petitioner argued that for the purposes of the IPR, claim terms should be given their ordinary and customary meaning.
• Petitioner noted that claim 10 contained a likely printing error, reciting a phase difference of "approximately 180°" where the prosecution history indicated it should be "within approximately 180°."
• Similarly, Petitioner asserted that claim 13 recited "with[in] 180°," which was understood to mean "within 180°" based on the patent's specification and prosecution history.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that while Jefferson was cited during the original prosecution of the ’507 patent, it was never substantively discussed or relied upon for any rejection by the Examiner. Petitioner contended it was presenting Jefferson in a new light with new arguments and expert testimony, which should preclude discretionary denial under §325(d).
• Petitioner also disclosed it was concurrently filing another IPR petition against the same patent but based on different prior art references. It requested that the Board institute review on all proposed grounds across both petitions, arguing the references and invalidity theories were distinct.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 10, 11, 13, and 15 of the ’507 patent as unpatentable.