NVIDIA Corp v. Polaris Innovations Ltd

1. Case Identification

• Case #: IPR2017-01500
• Patent #: 6,532,505
• Filed: May 30, 2017
• Petitioner(s): NVIDIA Corporation
• Challenged Claims: 1-18

2. Patent Overview

• Title: Universal Resource Access Controller
• Brief Description: The ’505 patent describes a "universal resource access controller" that functions as an intermediary between a requesting system (e.g., a processor) and a shared resource (e.g., memory). The controller receives an access request and generates a "sequenced command" by considering the resource's current state, the requested state, and its specific operating characteristics to manage access efficiently.

3. Grounds for Unpatentability

Ground 1: Obviousness over Chauvel - Claims 1-18 are obvious over Chauvel.

• Prior Art Relied Upon: Chauvel (Patent 6,253,297).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chauvel’s "traffic controller" for SDRAM memory inherently discloses the limitations of the challenged claims. Chauvel's controller receives memory access requests and, to reduce latency, generates a sequence of commands (e.g., precharge, activate, read/write). This process considers the memory's current state (e.g., active row), the requested state (the next pending request), and specific operating parameters like CAS latency. Petitioner contended this maps directly to the ’505 patent’s method of generating a "sequenced command."
  • Motivation to Combine (Modify): Although a single-reference ground, the core of the argument rested on modifying Chauvel's memory-specific controller to be "universal." Petitioner asserted a person of ordinary skill in the art (POSITA) would be motivated to do so because Chauvel itself teaches its controller "may be used in various other contexts." A POSITA would recognize that applying Chauvel's efficiency-improving techniques across different computer resources would reduce the number of separate controller designs, decrease die size, and enable more efficient pipelining.
  • Expectation of Success: Petitioner implicitly argued success was expected, as adapting a known, efficient control methodology from memory management to other standard computer resources was a predictable design choice for improving overall system performance.

Ground 2: Obviousness over Chauvel and Ramanujan - Claims 3-13, 16, and 18 are obvious over Chauvel in view of Ramanujan.

• Prior Art Relied Upon: Chauvel (Patent 6,253,297), Ramanujan (Patent 5,202,973).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground specifically addressed claims requiring a multiprocessor system and/or multiple shared memory modules. Chauvel provides the core controller functionality as detailed in Ground 1. Ramanujan, which was well-known at the time, explicitly discloses a multiprocessor computer system where multiple processors access multiple shared memory modules through a central memory controller. Ramanujan was cited to supply the multiprocessor and multi-memory environment that is a feature of these specific claims.
  • Motivation to Combine: Petitioner argued a POSITA seeking to improve performance in a known multiprocessor architecture (as taught by Ramanujan) would have been motivated to incorporate a more efficient memory controller. Chauvel’s advanced, latency-reducing controller would be an obvious choice to improve the bandwidth and speed of Ramanujan’s system. The combination represented the application of an improved component (Chauvel's controller) into a standard system architecture (Ramanujan's multiprocessor environment).
  • Expectation of Success: Success would be highly expected, as the modification was straightforward. It would involve connecting additional processors to Chauvel's system bus and adding identical, known circuitry to manage additional memory modules—both predictable and well-understood engineering tasks.

Ground 3: Obviousness over Paluch and Hughes - Claims 1-7 and 11-18 are obvious over Paluch in view of Hughes.

• Prior Art Relied Upon: Paluch (Patent 5,987,574), Hughes (Patent 5,784,582).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Paluch, which was considered during prosecution, teaches a memory controller that arbitrates requests for SDRAM and uses operating parameters and the current state of memory (e.g., the last-accessed bank) to generate commands. However, Petitioner contended that Paluch fails to explicitly teach using the requested state of the resource. Hughes was argued to cure this deficiency by disclosing a controller that analyzes a queue of pending requests—considering their location, size, and type—to intelligently select the next request to execute in order to optimize the memory pipeline. This selection of a "next requester" is equivalent to using the "requested state."
  • Motivation to Combine: A POSITA would combine the teachings because both Paluch and Hughes aim to increase the speed and efficiency of memory access. Paluch teaches efficiency via bank-switching, while Hughes teaches efficiency via intelligent request ordering. A POSITA would be motivated to combine Hughes's superior request-scheduling logic with Paluch’s bank arbitration system to create a controller more efficient than either taught alone.
  • Expectation of Success: The combination was presented as a predictable design choice. A POSITA would have reasonably expected success in supplementing or replacing Paluch's next-command selection logic with the more advanced, performance-enhancing logic described in Hughes.
• Additional Grounds: Petitioner asserted an additional obviousness challenge against the same claims based on Paluch in view of Chauvel, arguing Chauvel could also supply the "requested state" limitation.

4. Key Claim Construction Positions

• "universal resource access controller": Petitioner argued for the construction "a controller configurable to control access to any available resource, shared or not." This broad construction was critical to applying prior art memory controllers, like Chauvel, to the patent’s "universal" claims, asserting that a POSITA would find it obvious to adapt the memory controller for other resources.
• "sequenced command": Petitioner proposed the construction "multiple resource request commands juxtaposed within a unitary structure with the appropriate timing between the individual commands." This construction was used to map the sequences of discrete hardware-level commands (e.g., RAS, CAS, precharge) disclosed in the prior art to the unitary "sequenced command" recited in the claims.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-18 of the ’505 patent as unpatentable.