PTAB

IPR2017-01566

Micron Technology Inc v. Lone Star Silicon Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Low Dielectric Constant Etch Stop Layers in Integrated Circuit Interconnects
  • Brief Description: The ’330 patent describes integrated circuit interconnect structures manufactured using a dual damascene process. The purported invention is the use of silicon nitride (SiN) etch stop layers that have a low dielectric constant (below 5.5) to reduce parasitic capacitance and improve signal transmission speed.

3. Grounds for Unpatentability

Ground 1: Obviousness over Watatani and Tanaka - Claims 1, 2, 5-7, and 10 are obvious over Watatani in view of Tanaka.

  • Prior Art Relied Upon: Watatani (Patent 6,153,511) and Tanaka (1999 Symposium on VLSI Technology).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Watatani disclosed all elements of the challenged claims except for the specific requirement that the silicon nitride etch stop layer has a dielectric constant below 5.5. Watatani taught a conventional dual damascene interconnect structure, which was nearly identical to the "PRIOR ART" figure in the ’330 patent, including the use of silicon nitride etch stop layers. Watatani also identified the problem of "stray capacitance" caused by materials with a large dielectric constant, which degrades signal transmission. Petitioner asserted that Tanaka, a technical paper addressing the exact same problem, supplied the missing limitation. Tanaka explicitly taught that the "high permittivity of SiN" in conventional dual damascene processes degraded performance due to parasitic capacitance. To solve this, Tanaka developed and disclosed a process for forming a low-k silicon nitride etch stop layer with a dielectric constant of 5.4, which is below the claimed 5.5 threshold.
    • Prior Art Mapping (Dependent Claims): For claim 2, which added the limitation that the etch stop layer is a "multilayer structure," Petitioner argued that Watatani itself disclosed using an etch stop layer with "three or more layers" of silicon nitride. Petitioner contended this was a well-known technique to improve film uniformity and reduce pinhole defects, making its application an obvious design choice to a Person of Ordinary Skill in the Art (POSA). For claims 5 and 10, which specified conductor core materials like copper, Petitioner noted that Watatani disclosed copper ("Cu") for its conductor cores.
    • Motivation to Combine: Petitioner argued a POSA would have been motivated to combine the references because they were in the same field of dual damascene interconnects and addressed the identical, well-known problem of performance degradation from parasitic capacitance. Both references described the same conventional structure using the same materials (silicon nitride, silicon oxide, copper). A POSA, reading Watatani's identification of the problem, would have looked to the art for a solution and found Tanaka's explicit disclosure of a low-k silicon nitride film designed specifically to solve that problem in that very type of structure. The motivation was to replace the standard etch stop layer in Watatani’s structure with Tanaka’s improved low-k version to achieve better performance and reduced signal delay.
    • Expectation of Success: A POSA would have had a reasonable expectation of success because Tanaka’s low-k silicon nitride film was specifically designed for use in the conventional dual damascene structures described by Watatani. Tanaka reported "superior process results and film properties" for its low-k layer, stating it "should be the solution to realize Cu damascene interconnects for high performance VLSIs." Since the materials, purpose, and structural context were identical in both references, a POSA would expect the combination to work for its intended purpose.

4. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1, 2, 5-7, and 10 of the ’330 patent as unpatentable.