PTAB

IPR2017-01597

Micron Technology Inc v. Lone Star Silicon Innovations LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Core Cell Structure and Corresponding Process for NAND-Type High Performance Flash Memory Device
  • Brief Description: The ’085 patent relates to NAND-type flash memory devices and their fabrication. The patent discloses a core cell structure intended to improve device reliability and simplify manufacturing by replacing a conventional stacked-gate select transistor with a non-stacked structure, which allows it to be formed using the same process steps as low-voltage transistors in the device’s periphery.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hemink - Claims 1, 3, 6, and 7 are obvious over Hemink.

  • Prior Art Relied Upon: Hemink (Japanese Application Publication # H8-64703).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hemink, which aims to improve the reliability and reduce the manufacturing complexity of NAND devices, discloses all limitations of the challenged claims. Independent claim 1 requires a core region with a select gate transistor and a periphery region with low and high voltage transistors, where the select gate and low voltage transistors have gate oxide and gate electrode layers of substantially the same thickness. Petitioner asserted that Hemink’s second embodiment explicitly teaches forming the select gate and low-voltage peripheral transistors from the same oxide film and the same polysilicon layer, resulting in layers of the same thickness. Dependent claim 3’s stacked memory cell structure and claim 6’s plurality of select transistors sharing a common word-line were argued to be disclosed in Hemink’s general description of NAND architecture.
    • Key Aspects: This ground relies on Hemink's second embodiment, which discloses a non-stacked select gate, aligning with Petitioner's proposed construction of the term "select gate transistor."

Ground 2: Obviousness over Hemink in view of Shudo - Claim 4 is obvious over Hemink in view of Shudo.

  • Prior Art Relied Upon: Hemink (Japanese Application Publication # H8-64703) and Shudo (Japanese Application Publication # H08-64787).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Hemink teaches every element of the base claim 1, including a high voltage transistor in the device periphery. However, Hemink does not specify a thickness for the high voltage transistor's gate oxide layer. Dependent claim 4 adds the limitation that this high voltage transistor has a gate oxide layer of "about 400 Å." Petitioner argued that Shudo remedies Hemink’s silence by disclosing a conventional high voltage transistor with a gate oxide layer of 40 nm (400 Å).
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references as a matter of routine design. Hemink provides the overall device architecture but leaves the high voltage gate oxide thickness unspecified. Shudo provides a known, conventional thickness for that specific component. A POSITA would have been motivated to use a thicker gate oxide, as taught by Shudo, to improve device reliability and prevent dielectric breakdown, a well-known issue in high voltage transistors. This combination was presented as a simple substitution of one known element for another to obtain predictable results.
    • Expectation of Success: Petitioner asserted a high expectation of success because Hemink’s process already forms the high voltage gate oxide layer in a separate step. Therefore, modifying this step to produce a conventional thickness as taught by Shudo would have been a straightforward and predictable adjustment for a POSITA.

Ground 3: Obviousness over Tsunoda - Claims 1, 3, and 7 are obvious over Tsunoda.

  • Prior Art Relied Upon: Tsunoda (Japanese Application Publication # H8-306889).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Tsunoda, which also seeks to reduce process steps in NAND device manufacturing, discloses the claimed invention. Tsunoda teaches a device with a core ("memory cell section") and a periphery, where the select gate, low voltage, and high voltage transistors all have a stacked-gate structure. Critically, Tsunoda discloses forming the gate oxide layer for the select gate and low voltage transistors in a single step to a thickness of about 16 nm. It further discloses forming their gate electrode layers from the same second polysilicon layer to a thickness of about 350 nm. Petitioner argued this directly meets the limitation in claims 1 and 7 that these respective layers are "substantially the same" thickness.
    • Key Aspects: This ground relies on the Patent Owner's broader construction of "select gate transistor," which encompasses the stacked-gate structures disclosed in Tsunoda.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including claim 4 over Tsunoda in view of Shudo, and claim 6 over Tsunoda in view of Hemink, relying on similar motivations to combine to add specific, known features to a base reference.

4. Key Claim Construction Positions

  • “select gate transistor” (claims 1, 3, 4, 6, 7): This term was central to the petition's strategy.
    • Petitioner argued the term should be construed to mean a transistor that is not of a stacked-gate structure with multiple polysilicon layers. This construction was based on statements in the ’085 patent’s specification and prosecution history, where the applicant allegedly disclaimed stacked-gate structures for the select gate transistor to distinguish over the prior art.
    • Petitioner noted that Patent Owner’s construction in co-pending litigation was broader, not limiting the term to a single gate electrode layer device (i.e., it could include stacked gates).
    • Petitioner strategically applied its own narrower construction to grounds based on Hemink (which discloses a non-stacked option) and the Patent Owner's broader construction to grounds based on Tsunoda (which discloses a stacked select gate) to argue that the claims were unpatentable under either interpretation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3, 4, and 6-7 of Patent 6,023,085 as unpatentable.