PTAB

IPR2017-01597

Micron Technology, Inc. v. Lone Star Silicon Innovations, LLC

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1. Case Identification

2. Patent Overview

  • Title: Core Cell Structure and Corresponding Process for NAND-Type High Performance Flash Memory Device
  • Brief Description: The ’085 patent relates to the structure and fabrication of NAND-type flash memory devices. It purports to improve device reliability and simplify manufacturing by replacing the conventional stacked-gate structure of a select gate transistor with a non-stacked structure resembling a conventional low-voltage transistor, thereby allowing them to be formed using the same process steps.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hemink - Claims 1, 3, 6, and 7 are obvious over Hemink.

  • Prior Art Relied Upon: Hemink (Japanese Patent Application Publication H8-64703).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hemink teaches all limitations of the challenged claims. Hemink discloses a NAND-type flash memory device with a core region (containing memory cells and select transistors) and a periphery region (containing low and high voltage transistors). Critically, Hemink describes two embodiments for improving reliability and simplifying fabrication. Both embodiments teach that the gate oxide layer and gate electrode layer of the select gate transistor and the low-voltage transistor are formed during the same process steps, resulting in substantially the same thickness. This directly maps onto the key limitation of independent claims 1 and 7. The petition asserted that Hemink’s first embodiment (stacked gate) meets the claims under the Patent Owner's broader construction of "select gate transistor," while the second embodiment (single gate) meets the claims under the Petitioner's narrower construction. Dependent claim 3 is met as Hemink details the standard stacked structure of a memory cell (tunnel oxide, floating gate, insulating layer, control gate). Dependent claim 6 is met because Hemink shows a conventional NAND layout where pluralities of select gate transistors share a common conductive word-line.

Ground 2: Obviousness over Hemink and Shudo - Claim 4 is obvious over Hemink in view of Shudo.

  • Prior Art Relied Upon: Hemink (Japanese Patent Application Publication H8-64703) and Shudo (Japanese Patent Application H08-64787).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted this combination renders claim 4 obvious. Hemink provides the base NAND-type device with a high voltage transistor in the periphery, but does not specify a gate oxide thickness. Claim 4 requires the high voltage transistor to have a gate oxide layer of "about 400 Å" (40 nm). Shudo was cited to supply this missing limitation, as it explicitly teaches a high voltage transistor with a 40 nm thick gate oxide layer for improved performance.
    • Motivation to Combine: A POSITA would combine Hemink and Shudo as a simple substitution of one known element for another to achieve a predictable result. Petitioner argued that the conventional thickness for a high voltage gate oxide layer at the time was approximately 50 nm (500 Å), as taught by Shudo. Therefore, substituting a 40 nm (400 Å) layer from Shudo into Hemink's device would be a routine design choice driven by market forces toward miniaturization and increased reliability. Shudo's teachings on using boron ion implantation to calibrate threshold voltage would further motivate its use to enhance the reliability of Hemink's device.
    • Expectation of Success: A POSITA would have a high expectation of success. The combination involves substituting a gate oxide layer of a well-understood thickness into a standard transistor structure. Since Hemink already forms its high voltage gate oxide layer in a separate step from other oxide layers, modifying its thickness would be a straightforward and predictable process.

Ground 3: Obviousness over Tsunoda - Claims 1, 3, and 7 are obvious over Tsunoda.

  • Prior Art Relied Upon: Tsunoda (Japanese Patent Application Publication H8-306889).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner presented Tsunoda as an alternative primary reference that renders the claims obvious, particularly under the Patent Owner's broader claim construction which allows for stacked select gate transistors. Tsunoda explicitly teaches a NAND-type flash memory device comprising a core "memory cell section" and a "periphery circuitry." Critically, Tsunoda discloses that its memory cell, select gate, low voltage, and high voltage transistors all have a stacked structure. Tsunoda explicitly states that the gate oxide layers for the select gate transistor and the low voltage transistor are the same (about 16 nm thick) and that their control gate electrode layers are also the same (about 350 nm thick), as they are formed in the same simplified process. This directly teaches the limitations of independent claims 1 and 7. Dependent claim 3 is met by Tsunoda's description of the stacked memory cell structure.
  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Tsunoda with Shudo for claim 4, and Tsunoda with Hemink for claim 6, relying on similar component substitution and conventional layout arguments.

4. Key Claim Construction Positions

  • "select gate transistor" (claims 1, 3, 4, 6, 7): This was the most critical disputed term.
    • Petitioner's Proposed Construction: "a select gate transistor that (a) is not formed using a dual core oxide process and (b) is not of a stacked gate structure with multiple polysilicon layers." Petitioner argued the patent’s specification and prosecution history show the invention's purpose was to eliminate the stacked structure of the select gate transistor to simplify fabrication.
    • Patent Owner's Apparent Construction: "a transistor configured to enable transistors in a word line," which does not exclude stacked gate structures.
    • Petitioner's Strategy: The petition argued its grounds were successful under either construction. Grounds 1 and 2 were argued to invalidate the claims under both constructions (using Hemink's different embodiments). Grounds 3-5 were argued to be successful even under the Patent Owner's broader construction, as Tsunoda explicitly teaches a stacked select gate transistor.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3-4, and 6-7 of Patent 6,023,085 as unpatentable.