PTAB

IPR2017-01637

LG Electronics Inc v. Broadcom Corp

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multistandard Video Decoder
  • Brief Description: The ’059 patent discloses a system and method for decoding a video stream that can be encoded according to one of several different standards (e.g., H.264, VC-1, MPEG). The system identifies the specific encoding standard by determining an identifier, such as a start code, within the packetized data and then selects the corresponding decoding process to apply.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 11-14, 17-19, 21-24, and 27-29 under 35 U.S.C. §102

  • Prior Art Relied Upon: Wise (Application # 2003/0156652).
  • Core Argument for this Ground: Petitioner argued that Wise, which describes a multi-standard video decoder system, discloses every element of the challenged claims. Independent claims 11 (method) and 21 (system) are structurally similar, with claim 21 explicitly reciting a first and second processor for different functions.
    • Prior Art Mapping: Petitioner asserted that Wise teaches a system that receives packetized data on a chip via its pipeline system. Wise’s “Start Code Detector,” identified as the claimed "first processor," determines an identifier (a start code for standards like MPEG, H.261, JPEG) that defines the encoding type. This detector then generates a "CODING_STANDARD Token." This token is passed to a downstream "Huffman Decoder and Parser," identified as the claimed "second processor," which uses the token to select the correct decoding program from a microcode ROM and decode the video data. Petitioner contended this process maps directly to the claimed steps of receiving data, determining an identifier, selecting a process based on the identifier, and decoding.
    • Key Aspects: Petitioner argued that Wise's disclosure of a multi-chip set, including a Spatial Decoder Chip and a Temporal Decoder Chip that could be integrated onto a single VLSI device, anticipates the dual-processor limitations of claim 21. Furthermore, Petitioner mapped dependent claim limitations to Wise, such as identifying start codes (claims 12, 22), matching byte sequences (claims 13, 23), and utilizing FLC/VLC processes for H.261 decoding (claims 17, 27).

Ground 2: Obviousness of Claims 15, 16, 18, 19, 25, 26, 28, and 29 under 35 U.S.C. §103

  • Prior Art Relied Upon: Wise (Application # 2003/0156652).
  • Core Argument for this Ground: Petitioner presented two main obviousness arguments based on Wise alone. First, it would have been obvious to modify Wise’s decoder to support newer standards like H.264 and VC-1 (recited in claims 15, 16, 25, 26). Second, it would have been obvious to combine Wise's distinct spatial and temporal decoder chips onto a single chip to meet limitations in claims 18, 19, 28, and 29.
    • Motivation to Combine: Petitioner argued that a person of ordinary skill in the art (POSITA) would be motivated to update Wise's functionality to include the latest, widely adopted video standards like H.264 and VC-1 to maintain commercial relevance. Wise itself expressly stated its system could be adapted for "any other standards or combination of standards," which Petitioner argued suggests this future modification. Regarding chip integration, Wise recognized the industry trend of decreasing chip counts through integration, suggesting the combination of its spatial and temporal decoders onto a single chip was a predictable design choice.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in updating Wise because the newer H.264 and VC-1 standards employed similar start-code prefixes and block-based hybrid coding techniques as the older standards (H.261, MPEG) that Wise was already designed to handle. Success in integrating the decoder chips was also predictable, as System-on-Chip (SoC) design was a well-understood field.

Ground 3: Obviousness of Claims 20 and 30 over Wise in view of Wiegand

  • Prior Art Relied Upon: Wise (Application # 2003/0156652) and Wiegand ("Overview of the H.264/AVC Video Coding Standard," IEEE Transactions, July 2003).
  • Core Argument for this Ground: This ground addresses the "deblocking process" limitation in claims 20 and 30. Petitioner argued that while Wise teaches various filtering operations, it does not explicitly disclose a deblocking filter. Wiegand, which describes the H.264 standard, teaches an in-loop deblocking filter as an integral part of the standard.
    • Motivation to Combine: The primary motivation was to properly and fully implement the H.264 standard in the Wise architecture, an update Petitioner argued was obvious under Ground 2. Because Wiegand teaches that a deblocking filter is a standard component of H.264 decoding, a POSITA implementing H.264 support in Wise would have been motivated to include this feature to achieve the known benefits of the standard.
    • Expectation of Success: A POSITA would have expected success because Wiegand explicitly describes the deblocking filter as a "well-known method of improving the resulting video quality." Its application and benefits were well-understood, making its integration into a decoder architecture like Wise a straightforward modification to improve performance when handling H.264 streams.

4. Relief Requested

  • Petitioner requested that the Board institute an inter partes review (IPR) for claims 11-30 of the ’059 patent and issue a final written decision finding those claims unpatentable under 35 U.S.C. §§ 102 and 103 and ordering their cancellation.