PTAB

IPR2017-01841

Taiwan Semiconductor Manufacturing Company Limited v. Godo Kaisha IP Bridge 1

Log In

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device
  • Brief Description: The ’501 patent is directed to a metal-insulator-semiconductor field-effect transistor (MISFET). The claimed device includes standard MISFET components such as an active region on a semiconductor substrate, a gate insulating film, a gate electrode, source/drain regions, and a silicon nitride film. The feature central to the patent’s allowance was a gate electrode that protrudes upward from the silicon nitride film.

3. Grounds for Unpatentability

Ground 1: Obviousness over Igarashi and Woerlee - Claims 1, 4, 7, 9-11, 14, 16-18, and 23-25 are obvious over Igarashi in view of Woerlee.

  • Prior Art Relied Upon: Igarashi (Application # 2002/0145156) and Woerlee (Patent 6,406,963).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that the combination of Igarashi and Woerlee renders all challenged claims obvious under 35 U.S.C. §103. The core of the argument was that Igarashi, which was not considered during prosecution, discloses every limitation of independent claim 1, including the supposedly novel feature of a gate electrode protruding above a surrounding silicon nitride film. Petitioner asserted that Figure 12 of Igarashi clearly illustrates a MISFET structure with a gate electrode (3) that is taller than the adjacent silicon nitride film (8). Igarashi’s specification further describes removing the silicon nitride film from the upper surfaces of the gate electrodes, which results in the protruding structure.

      For any ambiguity, Petitioner contended Woerlee provides supplemental teachings. Specifically, while Igarashi discloses forming an "active element region" using a "trench method," Woerlee explicitly details how to form such active regions within a semiconductor substrate, defined by shallow trench isolation (STI) structures. This addresses the limitation of "an active region made of a semiconductor substrate."

      Petitioner further mapped all challenged dependent claims to the prior art. For example:

      • Claim 7 requires a sidewall interposed between the gate electrode and the silicon nitride film. Igarashi was argued to disclose this with its sidewall film (7) located next to the gate electrode (3) and under the silicon nitride film (8).
      • Claim 9 adds an interlevel insulating film and a contact plug. Igarashi was shown to disclose an interlevel insulating film (9) and a contact electrode (6) that passes through the films to connect to the source/drain region.
      • Claim 10 recites an isolation region dividing the active region. Petitioner argued the combination of Igarashi’s trench method and Woerlee’s explicit STI disclosure teaches this structure.
      • Claim 14’s requirement for a polysilicon gate electrode was argued to be directly taught by Igarashi’s disclosure of a polysilicon film (3a).
      • Claim 25, which combines several of these dependent claim features, was therefore argued to be obvious for the same reasons.

    • Motivation to Combine (for §103 grounds): Petitioner asserted that a person of ordinary skill in the art (POSITA) would combine Igarashi and Woerlee for several reasons. Both references are in the same field of MISFET device manufacturing. Igarashi proposes using a "trench method" for device isolation, and Woerlee provides explicit, conventional instructions for implementing that method to create STI regions. A POSITA would combine these teachings to achieve the well-known and necessary benefit of electrically isolating transistor components to prevent current leakage and device cross-talk, which is a fundamental design goal. The combination represented the use of known techniques to improve a device in a predictable way.

    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success in combining the references. The formation of active regions within a substrate using STI was a standard, routine technique in semiconductor manufacturing at the time. Applying Woerlee's detailed implementation of this standard technique to the MISFET described in Igarashi would have been a straightforward modification yielding predictable, reliable results.

    • Key Aspects: The central thrust of the petition was that the sole feature distinguishing the claims over the prior art of record—the protruding gate electrode—was not novel and was, in fact, explicitly disclosed in prior art that the Examiner did not consider.

4. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 4, 7, 9-11, 14, 16-18, and 23-25 of the ’501 patent as unpatentable under §103.