PTAB

IPR2018-00063

Nanya Technology Corporation v. Lone Star Silicon Innovations, LLC

Log In

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Transistor with Trenched Gate
  • Brief Description: The ’061 patent discloses a metal-oxide-semiconductor field-effect transistor (MOSFET) device featuring a gate electrode buried inside a trench etched into a silicon substrate. This architecture purportedly improves device packing density, manufacturability, and performance by reducing lateral diffusion and improving surface topography for miniaturized integrated circuits.

3. Grounds for Unpatentability

Ground 1: Anticipation by Anderson - Claims 1, 3, 4, 11, 13, and 14 are anticipated by Anderson under 35 U.S.C. §102.

  • Prior Art Relied Upon: Anderson (Patent 5,300,447).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Anderson, which was not considered during the original prosecution, teaches all limitations of the challenged claims. Independent claims 1 and 11 recite a semiconductor transistor with a trench formed in the substrate between source and drain regions, a contiguous channel region beneath the trench, a contiguous insulating layer lining the trench, and a trenched gate electrode. Petitioner asserted that Anderson discloses a "recessed channel" MOS device with a "trench, or groove" that meets these limitations. Specifically, Anderson teaches forming a trench in a p-type substrate, creating N+ doped source/drain regions on either side, forming a channel under the trench, and lining the trench with a contiguous insulating layer. Petitioner contended that Anderson's disclosure of forming a dummy gate oxide layer followed by creating nitride sidewalls results in a contiguous insulating layer on the vertical and bottom surfaces of the trench. Finally, Anderson teaches filling the insulated trench with a polysilicon gate conductor.
    • Key Aspects: The argument for dependent claims 4 and 14, which require a separately formed "trench spacer dielectric layer" and "trench dielectric," relied on Anderson's disclosure of forming insulating sidewalls and a bottom oxide layer in distinct process steps.

Ground 2: Anticipation by Tanaka - Claims 1, 3, 11, and 13 are anticipated by Tanaka under §102.

  • Prior Art Relied Upon: Tanaka (Patent 5,408,116).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Tanaka discloses a "fine-structured MOS transistor" with a "grooved-gate" structure developed to suppress the punch-through effect, which anticipates the core features of the ’061 patent. Petitioner asserted that Tanaka teaches a transistor with a groove (trench) formed in a p-type silicon substrate between n-type source and drain regions. Tanaka expressly discloses oxidizing the gate groove to form a contiguous gate oxide layer on both the vertical sidewalls and the bottom surface. The groove is then filled with a polysilicon gate electrode. Petitioner contended that Tanaka's description of a channel region formed at the bottom of the gate trench, connecting the source and drain regions, meets the corresponding limitation of the ’061 patent.

Ground 3: Anticipation by Furukawa - Claims 1, 3, 11, and 13 are anticipated by Furukawa under §102.

  • Prior Art Relied Upon: Furukawa (Patent 5,998,835).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Furukawa, which teaches a MOSFET and manufacturing method concerned with scaling down devices, anticipates the challenged claims. Furukawa discloses a device with a trench etched into a silicon substrate separating source and drain diffusion layers. Petitioner asserted that Furukawa explicitly teaches coating the trench sidewalls and bottom surface with a dielectric layer (e.g., oxidized silicon) to form a contiguous insulating layer. Subsequently, a polysilicon conductor is deposited into the trench to form the gate electrode. Furukawa also discloses a device channel formed adjacent to the bottom of the trench and diffusion extensions that extend under the trench to connect to the channel, thereby forming a contiguous channel region as claimed.

  • Additional Grounds: Petitioner asserted alternative obviousness challenges under §103 for all claims based on Anderson, Tanaka, and Furukawa individually. These grounds argued that to the extent the prior art does not explicitly anticipate every limitation, any differences would have been obvious modifications. For instance, if the preamble of claim 11 ("an array of multiple device structures") is found limiting, Petitioner argued a POSA would be motivated to integrate the individual transistors taught by each reference into a large-scale array (e.g., a DRAM chip), as suggested by the references themselves.

4. Key Claim Construction Positions

  • Petitioner argued for a construction of terms in dependent claims 4 and 14 based on the doctrine of claim differentiation. Independent claims 1 and 11 recite a single "trench-to-gate insulating layer" that is "contiguous." Dependent claims 4 and 14 further recite "a trench spacer dielectric layer formed on the substantially upright vertical surfaces" and "a trench dielectric formed on the bottom surface."
  • Petitioner contended that to give these dependent claim limitations meaning, they must be construed as requiring the vertical and bottom dielectric layers to be separately formed structures, distinct from a single, uniformly created layer. This construction was central to arguing that prior art like Anderson, which describes forming sidewall and bottom insulators in different steps, meets the limitations of the dependent claims.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3, 4, 11, 13, and 14 of Patent 6,097,061 as unpatentable.