PTAB

IPR2018-00065

Nanya Technology Corp v. Lone Star Silicon Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method for Forming Uniformly Sized Spacers on Transistor Gate Arrangements
  • Brief Description: The ’611 patent discloses a manufacturing method for semiconductor devices aimed at improving precision control. The method uses non-operational "dummy" gate arrangements placed adjacent to operational transistor gates to address spacer width variations that arise from inconsistent gate density across a substrate.

3. Grounds for Unpatentability

Ground 1: Obviousness over Admitted Prior Art and Dummy Gate References - Claims 1-5, 8-12, and 15 are obvious over Admitted Prior Art in view of the Dummy Gate References.

  • Prior Art Relied Upon: Admitted Prior Art (“APA”) as described in the ’611 patent, and a collection of references termed “Dummy Gate References,” including Yonemaru (Japanese Patent Publication No. H2-37725), Haribuchi (Japanese Patent Publication No. H9-64195), Matthews (Patent 5,112,761), and Ukeda (Patent 6,130,139).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the APA, as acknowledged in the ’611 patent, discloses the core problem: transistor arrays with non-uniform spacer widths caused by uneven gate spacing. The Dummy Gate References each teach the solution: inserting non-operational or dummy gate structures to manipulate the topology and equalize spacing, thereby ensuring uniform spacer formation. The combination of the APA’s problem with the known solution from the Dummy Gate References renders the claimed method obvious. For example, claim 1 requires an operational gate and a non-operational gate to form spacers of approximately the same base width; the APA shows the gate structures and the problem, and the Dummy Gate References provide the non-operational gate as the solution.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would have been motivated to apply the well-known technique of using dummy gates, as taught by the Dummy Gate References, to solve the exact problem of non-uniform spacers identified in the APA. This combination would have been a straightforward application of a known solution to a known problem to achieve predictable, improved results.

Ground 2: Obviousness over Admitted Prior Art and Yonemaru - Claims 1-5, 8-12, and 15 are obvious over Admitted Prior Art in view of Yonemaru.

  • Prior Art Relied Upon: APA and Yonemaru (Japanese Patent Publication No. H2-37725).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Yonemaru alone teaches the entire inventive concept. Yonemaru explicitly recognizes that variations in gate electrode density cause non-uniform spacer widths and discloses using dummy gate electrodes in sparsely populated areas to achieve uniform spacer shapes. This teaching directly maps onto the allegedly novel features of the ’611 patent, such as configuring one gate arrangement to be operational and another to be non-operational to control spacer width.
    • Motivation to Combine: The problem of non-uniform gate spacers described in the APA was a known issue in the semiconductor industry. Yonemaru provides a direct and explicit solution. A POSITA would combine the teachings of Yonemaru with the APA because Yonemaru was designed to improve precisely the type of structure disclosed in the APA. Applying Yonemaru's technique to the APA device would be an obvious path to improving device uniformity.

Ground 3: Obviousness over Yonemaru, Haribuchi, and Weste - Claims 1-5 and 8-12 are obvious over Yonemaru in view of Haribuchi and Weste.

  • Prior Art Relied Upon: Yonemaru (Japanese Patent Publication No. H2-37725), Haribuchi (Japanese Patent Publication No. H9-64195), and Weste (a treatise on CMOS VLSI design).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addresses a minor process variation. Yonemaru teaches the core concept of using dummy gates for spacer uniformity. Haribuchi and Weste both teach a "typical silicon gate process" where any exposed gate oxide film (in areas where no gate is formed) is removed before the subsequent dielectric layer is deposited. This ensures the later-formed spacers directly contact the silicon substrate. Petitioner argued that the process in Yonemaru could be viewed as not explicitly removing this oxide film. The combination remedies this by substituting Yonemaru’s gate formation process with the conventional process from Haribuchi/Weste.
    • Motivation to Combine: A POSITA would recognize that whether to remove the exposed gate oxide film before spacer formation was a well-known design choice with predictable consequences. Substituting the gate formation process in Yonemaru with the conventional, advantageous process taught by Haribuchi and Weste would have been an obvious modification to ensure direct spacer-to-substrate contact, a known desirable feature.

4. Key Claim Construction Positions

  • “transistor gate arrangement(s)” versus “polysilicon line”: Petitioner argued that a POSITA would understand the term “transistor gate arrangement” (recited in claims 1 and 8) to require more than a simple conductive line. It implies a functional structure, including a gate conductor and an underlying thin oxide layer, capable of controlling current. This construction distinguishes it from the term “polysilicon line” (recited in claim 15), which Petitioner contended is a broader term for a conductive line that does not necessarily constitute a transistor gate. This distinction was argued as relevant to the scope of the independent claims.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-5, 8-12, and 15 of the ’611 patent as unpatentable.