PTAB

IPR2018-00065

Nanya Technology Corporation v. Lone Star Silicon Innovations, LLC

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1. Case Identification

2. Patent Overview

  • Title: Method for Forming Substantially Uniformly Sized Spacers on Transistor Gate Arrangements
  • Brief Description: The ’611 patent discloses a method for manufacturing semiconductor devices with improved precision. The method addresses non-uniformity in the width of dielectric spacers formed on the sidewalls of transistor gates by introducing non-operational ("dummy") gate arrangements to normalize the spacing and density of gate structures, thereby ensuring the resulting spacers have a consistent base width.

3. Grounds for Unpatentability

Ground 1: Obviousness over Admitted Prior Art and Dummy Gate References - Claims 1-5, 8-12, and 15 are obvious over Admitted Prior Art in view of the Dummy Gate References.

  • Prior Art Relied Upon: Admitted Prior Art (APA) as described in the ’611 patent, in combination with a collection of references termed the "Dummy Gate References," which include Haribuchi (Japanese Patent Publication No. H9-64195), Yonemaru (Japanese Patent Publication No. H2-37725), Matthews (Patent 5,112,761), Ukeda (Patent 6,130,139), and Narita (Patent 5,410,161).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the ’611 patent’s APA explicitly describes the problem of non-uniform spacer widths resulting from variations in gate electrode density (i.e., some areas being densely populated while others are sparse). The Dummy Gate References collectively taught the well-known solution of using non-operational, or dummy, gate structures to manipulate the topology of a semiconductor substrate. Specifically, these references disclosed inserting dummy structures to create more uniform spacing between features, which directly addresses the problem identified in the APA.
    • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSA) would have been motivated to apply the known technique from the Dummy Gate References to the device described in the APA. The motivation was to solve the known problem of non-uniform spacer width by using a predictable and established method—inserting dummy gates—to improve process control and device uniformity.
    • Expectation of Success (for §103 grounds): A POSA would have had a reasonable expectation of success because applying the dummy gate technique was a known method for improving semiconductor devices in predictable ways, such as controlling feature dimensions by manipulating device topology.

Ground 2: Obviousness over Admitted Prior Art and Yonemaru - Claims 1-5, 8-12, and 15 are obvious over Admitted Prior Art in view of Yonemaru.

  • Prior Art Relied Upon: Admitted Prior Art (APA) and Yonemaru (Japanese Patent Publication No. H2-37725).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Yonemaru, which was not considered during prosecution, teaches the precise solution claimed in the ’611 patent. Yonemaru identified the same problem of non-uniform spacer width due to varied gate density and disclosed the same solution: forming dummy gate electrodes in sparsely populated areas to ensure uniform spacer shape and size across the device. Petitioner argued that Yonemaru discloses forming a dummy gate that is equidistant from adjacent operational gates, thereby creating the uniform spacing necessary to form spacers with the same width, directly mapping to the core limitations of claim 1.
    • Motivation to Combine (for §103 grounds): Invoking KSR, Petitioner argued that there was a known problem (non-uniform spacers, as described in the APA) for which Yonemaru provided an obvious solution. A POSA, faced with the problem in the APA, would have been motivated to look to known techniques and would have found Yonemaru's teaching of using dummy gates to be a direct and obvious solution to implement.
    • Expectation of Success (for §103 grounds): Success was expected because Yonemaru explicitly taught that its dummy electrode technique would make the width of the low-concentration diffusion layer uniform, allowing for the formation of transistors with the same characteristics.

Ground 3: Obviousness over Yonemaru, Haribuchi, and Weste - Claims 1-5 and 8-12 are obvious over Yonemaru in view of Haribuchi and Weste.

  • Prior Art Relied Upon: Yonemaru (Japanese Patent Publication No. H2-37725), Haribuchi (Japanese Patent Publication No. H9-64195), and Weste (a 1985 treatise on CMOS VLSI design).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed a subtle process variation. The process in Yonemaru does not remove the exposed gate oxide film in areas where no gate is formed. In contrast, Haribuchi and the Weste treatise described a "typical" or "conventional" silicon gate formation process where this exposed oxide film is removed before the dielectric layer for the spacers is deposited. This allows the subsequently formed spacers to directly contact the silicon substrate. Petitioner argued for the obviousness of substituting the gate formation process of Haribuchi/Weste into the overall method of Yonemaru.
    • Motivation to Combine (for §103 grounds): Petitioner asserted that whether to remove the exposed gate oxide film was a mere design choice for a POSA. A POSA would have been motivated to substitute the conventional gate formation process taught by Haribuchi and Weste into the Yonemaru method to achieve the benefits of both—the uniform spacing from Yonemaru's dummy gates and the direct substrate contact for spacers from Haribuchi's process.
    • Expectation of Success (for §103 grounds): A POSA would have expected success, as this was a simple substitution of one known, conventional fabrication step for another, leading to predictable results.

4. Key Claim Construction Positions

  • Petitioner argued for a distinction between the terms "transistor gate arrangement(s)" (recited in claims 1 and 8) and "polysilicon line" (recited in claim 15).
    • Petitioner asserted that a "transistor gate arrangement" requires more than just a conductive line; it must include the structural elements to function as a gate that controls current flow in a transistor (e.g., a gate conductor over a thin oxide layer).
    • In contrast, a "polysilicon line" could be merely a conductive line without the underlying structures needed for transistor operation. This distinction was critical to Petitioner's argument that certain prior art disclosing only simple polysilicon lines did not teach the "transistor gate arrangement" limitation.

5. Relief Requested

  • Petitioner requested that the Board institute an inter partes review (IPR) and cancel claims 1-5, 8-12, and 15 of Patent 6,103,611 as unpatentable.