PTAB

IPR2018-00362

SK Hynix Inc v. Netlist Inc

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1. Case Identification

2. Patent Overview

  • Title: MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND METHOD OF OPERATION
  • Brief Description: The ’907 patent relates to high-capacity memory modules that use distributed data buffers to manage electrical load. The invention aims to solve the problem of system slowdown caused by adding more memory devices by selectively connecting active memory ranks to the memory controller while isolating the electrical load from inactive ranks.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ellsberry - Claims 1-29 and 58-65 are obvious over Ellsberry.

  • Prior Art Relied Upon: Ellsberry (Application # 2006/0277355).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ellsberry disclosed every limitation of the challenged claims, asserting the reference was not considered during prosecution. Both the ’907 patent and Ellsberry identified the same problem of increased electrical load on memory modules and proposed using distributed buffers to solve it. Petitioner mapped Ellsberry’s "memory bank switches" to the claimed "buffer circuits," noting they are functionally identical. These switches are placed on a printed circuit board (PCB) between memory devices and the edge connector to selectively connect different memory banks (e.g., via "Port A" or "Port B") to the memory controller. This selective connection isolates the electrical load of unused memory devices from the system bus, directly teaching the core concept of the ’907 patent. Ellsberry’s control unit (ASIC 204) was mapped to the claimed "module control circuit," as it receives commands and generates the necessary control signals to manage the switches and direct data to the correct memory bank. Petitioner asserted this ground as obviousness primarily to avoid unnecessary disputes over whether Ellsberry fully anticipated the claims.
    • Motivation to Combine (for §103 grounds): Not applicable, as this is a single-reference ground.
    • Expectation of Success (for §103 grounds): Not applicable.

Ground 2: Obviousness over Ellsberry and JEDEC Standard - Claims 1-29 and 58-65 are obvious over Ellsberry in view of JESD21-C.

  • Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and JESD21-C (JEDEC Standard No. 21-C).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground was presented as an alternative, arguing that to the extent Ellsberry was viewed as not explicitly teaching the claimed PCB and edge connector details, these features were well-known and disclosed by JESD21-C. JESD21-C is an industry standard for DDR SDRAM Dual In-Line Memory Modules (DIMMs) and explicitly describes the standard PCB form factor, including an edge connector with electrical contacts for releasably coupling to a computer system socket. Combining this standard module structure with Ellsberry’s buffering system would result in the claimed invention.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Ellsberry's novel capacity-expanding technology with the standard DIMM form factor described in JESD21-C. This combination would be motivated by the desire to ensure compatibility with existing systems, leverage well-known and reliable manufacturing techniques, and expand the potential market for a product embodying Ellsberry's technology.
    • Expectation of Success (for §103 grounds): The combination involved implementing a new circuit design on a standard, predictable hardware platform, leading to a high and predictable expectation of success.

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on combining Ellsberry with other references to teach specific dependent claim features. These included: Ellsberry in view of Halbert (Patent 7,024,518) for claims requiring signals that indicate the direction of data flow; Ellsberry in view of Ruckerbauer (Patent 7,334,150) for claims related to specific integrated circuit layouts with separate connections; and Ellsberry in view of Stone (a 1982 book) for claims requiring the use of tristate buffers in the data paths.

4. Key Claim Construction Positions

  • "isolate memory device load": Petitioner proposed this term, which appears in all asserted independent claims, should be construed as “electrically separate memory device load.” This construction was supported by prior Board interpretations of a parent patent and testimony from the Patent Owner's own expert in related litigation.
  • "Fork-in-the-road" vs. "Straight-line" Interpretation: Petitioner argued the claims encompass two possible memory device configurations. The "fork-in-the-road" view, supported by the patent's figures, places different memory device ranks on separate data paths branching from a buffer. The "straight-line" view, allegedly advanced by the Patent Owner in parallel litigation, places all devices on a single data path. Petitioner preemptively argued that Ellsberry teaches embodiments corresponding to both configurations, making the claims obvious regardless of the adopted construction.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-29 and 58-65 of the ’907 patent as unpatentable under 35 U.S.C. §103.