SK Hynix Inc v. Netlist Inc

1. Case Identification

• Case #: IPR2018-00363
• Patent #: 9,606,907
• Filed: December 22, 2017
• Petitioner(s): SK Hynix Inc., SK Hynix America Inc., and SK Hynix Memory Solutions Inc.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 30-57

2. Patent Overview

• Title: MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND METHOD OF OPERATION
• Brief Description: The ’907 patent relates to a memory module architecture designed to manage the increased electrical load from having numerous memory devices. The invention uses distributed data buffers, or transmission circuits, to selectively connect ranks of memory devices to a memory controller, thereby isolating the electrical load of unused ranks to improve overall system performance and speed.

3. Grounds for Unpatentability

Ground 1: Obviousness over Ellsberry - Claims 30-57 are obvious over Ellsberry

• Prior Art Relied Upon: Ellsberry (Application # 2006/0277355).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ellsberry teaches the fundamental concept of the ’907 patent. Both documents identify the problem of increased electrical load on memory modules and propose the same solution: using distributed buffers along the module's edge to reduce load. Petitioner asserted that Ellsberry’s "memory bank switches" are functionally identical to the ’907 patent’s "buffer circuits." These switches selectively connect groups of memory devices to the memory controller, creating distinct data paths and isolating the load of unused memory devices. Petitioner contended that Ellsberry’s figures and disclosure directly map to the key limitations of independent claims 30 and 43, including the module control circuit, memory devices grouped into sets, and buffer circuits that create selectable data paths in a "fork-in-the-road" manner.
  • Key Aspects: Petitioner asserted that Ellsberry's disclosure is so similar to the ’907 patent that it likely anticipates the claims, but the challenge was framed as obviousness under 35 U.S.C. §103 to preempt unnecessary disputes.

Ground 2: Obviousness over Ellsberry and JESD21-C - Claims 30-57 are obvious over Ellsberry in view of JESD21-C

• Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and JESD21-C (JEDEC Standard No. 21-C).
• Core Argument for this Ground:
  • Prior Art Mapping: This alternative ground contended that to the extent Ellsberry might be found insufficient in disclosing conventional memory module features, such as a printed circuit board (PCB) with a standard edge connector, the JESD21-C reference supplies these elements. JESD21-C is an established industry standard for DDR SDRAM Dual In-Line Memory Modules (DIMMs) and explicitly details the required physical and electrical interface specifications, including the edge connector contacts and their layout for providing conductivity to the system socket.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Ellsberry’s novel capacity-expanding technology with the standard DIMM form factor defined in JESD21-C. This combination would be motivated by the desire to ensure product compatibility, interoperability with existing computer systems, and broad market acceptance, which are all benefits of adhering to industry standards.
  • Expectation of Success: Combining a new circuit architecture onto a standard, well-defined physical module was a routine and predictable design choice for memory engineers, carrying a high expectation of success.

Ground 3: Obviousness over Ellsberry and Stone - Claims 39-42 and 45-57 are obvious over Ellsberry in view of Stone

• Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and Stone (Microcomputer Interfacing by H. Stone, 1982).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground specifically addressed dependent claims requiring "tristate buffers" for implementing the read and write data paths. Petitioner argued that while Ellsberry discloses "bidirectional drivers," it would have been obvious to a POSITA to implement these drivers using tristate buffers as taught by Stone. Stone was cited as a foundational text that explicitly teaches using tristate drivers for interfacing components on a shared bus, noting they are particularly "suitable for driving several taps on a transmission line," a configuration present in Ellsberry’s design.
  • Motivation to Combine: A POSITA would be motivated to use the tristate buffers taught by Stone to implement Ellsberry's bidirectional drivers to achieve a reliable and efficient interface. This was a well-known and common engineering solution for managing data flow on buses with multiple connected devices, preventing signal contention and ensuring data integrity.
  • Expectation of Success: Using tristate buffers to create bidirectional drivers was a fundamental and predictable technique in digital circuit design at the time, ensuring a high expectation of success.

• Additional Grounds: Petitioner asserted an additional obviousness challenge for claim 36 over Ellsberry in view of Ruckerbauer (Patent 7,334,150) to address a specific interpretation of coupling subsets of memory devices to a central controller.

4. Key Claim Construction Positions

• "isolate memory device load": Petitioner argued that the broadest reasonable construction for this term is "electrically separate memory device load." This position was supported by a prior Board interpretation of the same term in the parent ’185 patent and by the Patent Owner’s own expert testimony in a related ITC litigation.
• "Fork-in-the-road" vs. "Straight-line" Interpretation: A central point of contention was the data path architecture. Petitioner contended the ’907 patent discloses a "fork-in-the-road" structure where a buffer routes data to one of two or more distinct paths, electrically isolating the devices on the unselected path(s). Petitioner argued that its invalidity contentions prevail even under the Patent Owner’s narrower "straight-line" interpretation (where selected and unselected memory devices reside on the same data path and are selected via chip-select signals), but that the "fork-in-the-road" construction is the correct one.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 30-57 of the ’907 patent as unpatentable.