PTAB

IPR2018-00363

SK Hynix Inc v. NeTLIst Inc

Case #: IPR2018-00363
Patent #: 9,606,907
Filed: December 22, 2017
Petitioner(s): SK HYNIX INC., SK HYNIX AMERICA INC., and SK HYNIX MEMORY SOLUTIONS INC.
Patent Owner(s): NETLIST, INC.
Challenged Claims: 30-57

Title: MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND METHOD OF OPERATION
Brief Description: The ’907 patent relates to high-capacity memory modules. It addresses the problem that increasing the number of memory devices on a module increases electrical load, which can slow down system performance. The disclosed solution is a memory module with data buffers distributed along its edge, which isolate the electrical load of memory devices and selectively connect only the ranks of memory currently in use to the memory controller.

Prior Art Relied Upon: Ellsberry (Application # 2006/0277355).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Ellsberry is remarkably similar to the ’907 patent, as both identify the same problem of electrical load in high-capacity memory modules and disclose the same solution. Ellsberry teaches using distributed “memory bank switches” (the claimed buffer circuits) along the edge of a memory module to reduce load and selectively connect different memory banks to the system controller. Petitioner asserted that Ellsberry’s control unit (204), memory bank switches (206, 208), and selectable data paths (Port A/B) map directly onto the limitations of independent claims 30, 43, and 53. The mapping was argued to cover both the "fork-in-the-road" architecture and a "straight-line" architecture, where different memory devices on the same data path are selected.
- Key Aspects: Petitioner emphasized that Ellsberry was not considered during the original prosecution of the ’907 patent, despite its strong relevance.

Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and JESD21-C (JEDEC Standard No. 21-C, Jan. 2002).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that to the extent Ellsberry was deemed not to sufficiently disclose the claimed printed circuit board (PCB) with an edge connector, JESD21-C explicitly supplies this teaching. JESD21-C is a foundational industry standard that defines the physical and electrical specifications for DDR SDRAM Dual In-Line Memory Modules (DIMMs), including the standard PCB form factor, edge connector, and pin-outs for providing electrical conductivity for control and data signals.
- Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings to implement Ellsberry's novel capacity-expanding technology on a standard, industry-compliant DIMM form factor. This would ensure broad market compatibility and interoperability, a primary goal in memory module design.
- Expectation of Success: The combination was presented as a predictable arrangement of known elements, applying a standard DIMM architecture from JESD21-C to the memory system of Ellsberry, with each element performing its known function.

Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and Ruckerbauer (Patent 7,334,150).
Core Argument for this Ground:
- Prior Art Mapping: This ground specifically addressed the limitations of dependent claim 36, which requires the module control circuit to have multiple input/output connections coupled to different subsets of memory devices. Petitioner asserted Ruckerbauer teaches a memory module with a control circuit mounted in the middle of the PCB, from which command and address signals run on separate lines to memory chips on the left and right sides of the controller. This explicitly teaches the claimed "subsets" of memory devices being coupled to distinct connections.
- Motivation to Combine: A POSITA would be motivated to implement Ellsberry's module with the separate control line architecture of Ruckerbauer. This approach would simplify the connections on a densely populated PCB and reduce the capacitive loading on the control lines, which is necessary to achieve the high signal speeds required for modern memory.
- Expectation of Success: Both references are in the same field of memory module design, and combining their respective teachings on component layout and signal routing was argued to be a predictable design choice to improve performance.

Prior Art Relied Upon: Ellsberry (Application # 2006/0277355) and Stone (Microcomputer Interfacing, 1982).
Core Argument for this Ground:
- Prior Art Mapping: For claims that require "tristate buffers" to implement read/write data paths, Petitioner argued it would have been obvious to use this well-known technology to realize Ellsberry's bidirectional drivers. Stone, a foundational textbook on computer interfacing, explicitly teaches that tristate drivers are suitable for driving multiple taps on a transmission line. Ellsberry’s design, with data buses on Ports A and B having multiple taps for each memory device, is such a transmission line.
- Motivation to Combine: A POSITA would have been motivated to implement the bidirectional drivers in Ellsberry's design using the tristate buffers disclosed in Stone. This was presented as a standard, reliable, and efficient method for creating the necessary interface circuit to drive data to and from the memory devices.
- Expectation of Success: Using a fundamental, well-known component like a tristate buffer to implement a higher-level functional block (a bidirectional driver) was described as a routine engineering task with predictable results.

"isolate memory device load": Petitioner proposed the construction “electrically separate memory device load.” This was based on the Board's prior interpretation of the similar term "selectively isolate" in a related patent and the patent owner's expert testimony in parallel litigation.
"the first memory devices output or receive each N-bit wide data signal": Petitioner argued this phrase should not be limited to a single rank of memory devices. The claim language only requires that the "memory devices" together handle the N-bit wide data signal, which is consistent with the specification.
"Fork-in-the-road" vs. "Straight-line" Interpretation: Petitioner acknowledged a dispute in parallel litigation where the Patent Owner argued for a "straight-line" interpretation (where selected and non-selected devices are on the same data path). Petitioner contended that this dispute was immaterial because Ellsberry discloses embodiments that render the claims obvious under both the patent's disclosed "fork-in-the-road" interpretation and the Patent Owner's "straight-line" litigation position.

Petitioner requested the institution of an inter partes review and the cancellation of claims 30-57 of the ’907 patent as unpatentable under 35 U.S.C. §103.