PTAB

IPR2018-00364

SK Hynix Inc v. Netlist Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Module with Distributed Data Buffers and Method of Operation
  • Brief Description: The ’907 patent is directed to high-capacity memory modules, such as dual in-line memory modules (DIMMs), that use distributed data buffers. The technology aims to mitigate increased electrical loads that can slow system performance by isolating memory devices from the main system memory bus and creating selective data transmission paths.

3. Grounds for Unpatentability

Ground 1: Obviousness over Halbert and Amidi - Claims 1-29 and 58-65 are obvious over Halbert in view of Amidi.

  • Prior Art Relied Upon: Halbert (Patent 7,024,518) and Amidi (Application # 2006/0117152).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Halbert disclosed the core architecture of the ’907 patent, including a memory module with distributed data buffers (which Halbert calls "interface circuits") to isolate memory device loads from the system memory bus. Halbert’s design used a multiplexer/demultiplexer to create a "fork in the road," routing data to one of two memory ranks while isolating the other. While Halbert primarily showed a two-rank module, it explicitly stated that other numbers of ranks, such as four, were possible. Petitioner contended that Amidi taught a known method for expanding a memory module’s capacity from two ranks to four in a way that remains compatible with existing memory controllers. Amidi achieved this using a Complex Programmable Logic Device (CPLD) to receive two chip-select signals from a controller and generate four internal chip-select signals to activate one of the four ranks. The combination of Halbert’s load-isolating buffer architecture with Amidi’s rank-expansion technique allegedly rendered the challenged claims obvious.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Halbert and Amidi to increase the memory capacity of Halbert’s module, a constant goal in the industry. Halbert’s own disclosure that more ranks were possible would have prompted a POSITA to look for known, reliable methods for adding ranks, such as the one taught by Amidi. Amidi’s technique was advantageous because it allowed for doubling memory capacity using cheaper, lower-density devices while maintaining compatibility with existing memory controllers designed for fewer ranks.
    • Expectation of Success: The combination involved applying a known technique (Amidi’s rank expansion) to a known base system (Halbert’s buffered module) to achieve a predictable result (a higher-capacity buffered module). Implementing Amidi’s CPLD logic within Halbert’s module controller was a straightforward design choice with no technical barriers, yielding the expected benefits of increased capacity and continued load isolation.

Ground 2: Obviousness over Halbert, Amidi, and Ruckerbauer - Claims 9, 13, 23, 28, and 59-65 are obvious over Halbert and Amidi in further view of Ruckerbauer.

  • Prior Art Relied Upon: Halbert (Patent 7,024,518), Amidi (Application # 2006/0117152), and Ruckerbauer (Patent 7,334,150).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the Halbert-Amidi combination to address specific claim limitations related to a module control circuit having multiple distinct input/output connections coupled to corresponding subsets of memory devices. Halbert’s module controller was shown with a T-bus topology for command and address signals, where a single bus branches to the left and right sides of the module. Ruckerbauer taught an improved design for high-speed operation where the controller has separate, dedicated buses running to the left and right sides of the module. Petitioner argued that modifying the Halbert-Amidi combination to incorporate Ruckerbauer’s separate left/right bus architecture would have been an obvious design choice.
    • Motivation to Combine: A POSITA would be motivated to modify the Halbert-Amidi module with Ruckerbauer's bus design to achieve higher operating speeds. Ruckerbauer explicitly taught that its separate bus design was superior to conventional bus transfers at high speeds because it reduced loading effects and improved signal integrity. This modification directly addressed the goal of improving performance, a primary objective for memory system designers.
    • Expectation of Success: Implementing separate left and right buses from the module controller was a known technique for improving performance. A POSITA would have had a high expectation of success in applying this well-understood principle to the Halbert-Amidi architecture to create a faster, more robust high-capacity memory module.
  • Additional Grounds: Petitioner asserted additional obviousness challenges based on the Halbert-Amidi combination in further view of Stone (a textbook teaching the use of tristate buffers) for claims requiring tristate buffers, and Solomon (an application teaching latency-based timing) for claims requiring control of timing with a latency parameter.

4. Key Claim Construction Positions

  • "isolate memory device load": Petitioner argued this term’s broadest reasonable construction is "electrically separate memory device load." This position was supported by a prior Board interpretation of the parent patent and testimony from the Patent Owner’s expert in related litigation, where it was agreed that isolation requires electrical separation.

5. Key Technical Contentions

  • "Fork-in-the-road" vs. "Straight-line" Interpretation: Petitioner identified a potential claim interpretation dispute from parallel litigation. The patent specification describes a "fork-in-the-road" architecture where data paths to different memory ranks are electrically distinct. The Patent Owner allegedly argued for a "straight-line" interpretation where first and second memory devices are on the same data path. Petitioner contended that its invalidity arguments based on the prior art combinations rendered the claims obvious under either interpretation, making resolution of the dispute unnecessary for institution.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-29 and 58-65 of the ’907 patent as unpatentable under 35 U.S.C. §103.