PTAB

IPR2018-00560

Vizio Inc v. ATI Technologies ULC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: PARALLEL PIPELINE GRAPHICS SYSTEM
  • Brief Description: The ’506 patent describes a graphics processing chip architecture designed to improve performance. The system uses a back-end comprising multiple parallel processing pipelines, with each pipeline including a "unified shader" that is programmable to perform both color shading and texture shading operations.

3. Grounds for Unpatentability

Ground 1: Obviousness over Papakipos and Gibson - Claims 1-2 and 6-9 are obvious over Papakipos in view of Gibson.

  • Prior Art Relied Upon: Papakipos (Patent 6,532,013) and Gibson (Patent 6,750,867).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Papakipos disclosed all elements of the base graphics chip of claim 1 except for the use of multiple parallel pipelines and tiling. Papakipos taught a graphics chip with a front-end for processing geometry and a back-end for rasterization and shading. Crucially, Petitioner asserted that Papakipos’s “Shader Module 406” is a programmable “unified shader” capable of performing both color shading (e.g., calculating diffuse/specular colors) and texture shading by interweaving shading calculations and texture retrieval operations. Gibson was cited for its express teaching of using multiple parallel rendering devices (shaders) and dividing the screen into tiles to distribute the processing workload, thereby improving performance.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings to improve the performance of the Papakipos graphics pipeline. Petitioner contended that using parallel processing to accelerate graphics rendering was a well-known technique, and Gibson explicitly taught using parallel rendering devices and tiling for this purpose. A POSITA would have been motivated to apply Gibson’s established parallel architecture to the shader in Papakipos to achieve predictable performance gains and better load balancing.
    • Expectation of Success: Success was expected because both references operate in the same technical field of graphics processing pipelines. Implementing parallel shaders was considered routine engineering, and the benefits of such a combination were clearly articulated in Gibson and widely understood in the art.

Ground 2: Obviousness over Papakipos, Gibson, and Zhu - Claims 3-5 are obvious over Papakipos and Gibson in further view of Zhu.

  • Prior Art Relied Upon: Papakipos (Patent 6,532,013), Gibson (Patent 6,750,867), and Zhu (Patent 6,697,063).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the base combination of Papakipos and Gibson to address dependent claims 3-5, which added limitations related to Z-buffering. Petitioner argued that while Papakipos and Gibson provided the parallel pipeline architecture, Zhu supplied the specific buffer logic units recited in the claims. Zhu disclosed a “double-z” scheme that utilized a “z buffer logic unit,” a “color buffer logic unit,” and interfaces for early, late, and hierarchical Z-buffering to efficiently remove non-visible fragments from the processing pipeline.
    • Motivation to Combine: A POSITA would combine Zhu’s advanced Z-buffering techniques with the parallel pipeline of Papakipos and Gibson to further improve processing efficiency. Reducing the shading workload by culling occluded pixels early was a known method for optimization. Petitioner argued a POSITA would have been motivated to incorporate Zhu’s superior “double-z” scheme into the base system to “reduce[] raster/shading requirements,” a clear advantage identified by Zhu itself.
    • Expectation of Success: Adding well-understood buffering logic like that taught in Zhu to a standard graphics pipeline was a predictable and common design choice. Zhu’s components were designed to solve a known problem (inefficient shading of non-visible pixels) and would be expected to function as intended within the Papakipos/Gibson architecture.

Ground 3: Obviousness over Papakipos, Gibson, and Donham - Claims 1-2 and 6-9 are obvious over Papakipos, Gibson, and Donham.

  • Prior Art Relied Upon: Papakipos (Patent 6,532,013), Gibson (Patent 6,750,867), and Donham (Patent 6,980,209).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground was presented as an alternative to Ground 1 to preemptively address a narrower construction of "unified shader" potentially requiring a single, integrated circuit. While Petitioner maintained Papakipos’s shader met the limitation, it argued Donham’s “Pixel Shader 30” provided an even more explicit disclosure. Donham taught a shader with “Microblenders” and “Math Units” that constituted a single circuit architecture for executing the arithmetic operations for both color shading (blending values) and texture shading (bump mapping).
    • Motivation to Combine: A POSITA seeking to implement the unified shader functionality of Papakipos would have naturally looked to other known shader circuits, like Donham, for detailed implementation examples. Petitioner argued that implementing the Papakipos shader using the specific ALU-like circuitry disclosed in Donham would have been routine engineering, as all references were directed to the same graphics pipeline technology.
    • Expectation of Success: A POSITA would have had a high expectation of success because Donham’s shader performed the same functions as Papakipos’s shader. Integrating Donham’s more detailed circuit design into the Papakipos system was a matter of applying known design principles to achieve a predictable result.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) for claims 3-5 based on the four-way combination of Papakipos, Gibson, Donham, and Zhu, incorporating the arguments from all prior grounds.

4. Key Claim Construction Positions

  • "unified shader": This term was central to the petition. Petitioner argued that under the Broadest Reasonable Interpretation (BRI) standard, the plain and ordinary meaning should apply and that the “Shader Module 406” of Papakipos met this meaning. However, acknowledging that the Patent Owner argued for a narrower construction in a co-pending ITC case (requiring a "single shader circuit"), Petitioner presented Ground 3 (adding Donham) to demonstrate that the claims were obvious even under a more restrictive interpretation. Donham was used to explicitly show a single shader circuit with integrated "Microblenders" performing both shading types.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-9 of the ’506 patent as unpatentable under 35 U.S.C. §103.