PTAB

IPR2018-00999

Micron Technology v. North Star Innovations Inc

Log In

1. Case Identification

2. Patent Overview

  • Title: Complimentary Double Pumping Voltage Boost Converter
  • Brief Description: The ’875 patent relates to a voltage boosting circuit for integrated circuits. The invention purports to reduce output voltage distortion by using a complementary "double pumping" architecture that boosts the voltage twice during each clock cycle, rather than once as in the acknowledged prior art.

3. Grounds for Unpatentability

Ground 1: Anticipation - Claims 1 and 3 are anticipated by Foss.

  • Prior Art Relied Upon: Foss (Patent 5,267,201).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Foss discloses a voltage boosting circuit with the same symmetric, dual-portion architecture and functionality claimed in the ’875 patent. For claim 1, Petitioner mapped Foss’s transistors 1 and 2 to the claimed first and second switches, which are operated by opposite clock phase signals (φ2 and φ1). Foss’s capacitors 11 and 9 were mapped to the first and second capacitors, which are coupled to receive a boost signal derived from a common oscillator. For claim 3, Petitioner asserted that Foss’s transistors 5 and 6 directly correspond to the claimed third and fourth switches that couple the capacitors to the output terminal.

Ground 2: Obviousness over Core Circuit and Textbook - Claims 1-3 are obvious over Foss in view of Baker.

  • Prior Art Relied Upon: Foss (Patent 5,267,201) and Baker (a 1997 textbook, CMOS Circuit Design, Layout, and Simulation).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Foss teaches the core voltage pump circuit, while Baker teaches the specific implementation of the clock and boost signal generation circuitry. Baker disclosed using a common oscillator signal passed through two separate paths to generate opposite clock signals for a voltage pump. One path used a single inverter (an inverting buffer), and the other used a cascade of two inverters (a non-inverting buffer). Petitioner argued this combination explicitly teaches the "inverting buffer" and "non-inverting buffer" limitations of dependent claim 2, which drive the two symmetric portions of the boost circuit disclosed in Foss.
    • Motivation to Combine: A POSITA would combine Foss and Baker as both references are in the field of voltage boost circuits. Foss describes its circuit being driven by an oscillator but does not detail the oscillator's internal schematics. A POSITA seeking to implement Foss’s design would naturally consult a standard textbook like Baker for a conventional and well-known method to generate the required opposite-phase clock signals.
    • Expectation of Success: Petitioner asserted a high expectation of success, as the combination merely involved applying a known, standard clock generation technique to a known voltage pump circuit to achieve predictable results.

Ground 3: Obviousness over Core Circuit and Journal Article - Claims 1-3 are obvious over Foss in view of Rabii.

  • Prior Art Relied Upon: Foss (Patent 5,267,201) and Rabii (a 1997 IEEE journal article, A 1.8V Digital-Audio Sigma-Delta Modulator in 0.8-µm CMOS).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative secondary reference to Baker for supplying the clock generation details. Petitioner argued that Rabii’s boosted clock driver circuit also taught a standard method for generating two opposite clock signals from a common input clock signal using a cascade of two inverters. Applying Rabii’s clock generation circuit to Foss’s voltage pump would render the claimed invention obvious, with Rabii’s left inverter functioning as the "inverting buffer" and the two-inverter cascade functioning as the "non-inverting buffer" required by claim 2.
    • Motivation to Combine: A POSITA would combine the references because they address the same technical problem and describe circuits with substantially similar structures and functions. Given Foss’s reliance on an undetailed oscillator, a POSITA would have been motivated to look to resources like the Rabii paper for a compatible and efficient clock generation circuit. Connecting the inverters in Foss to form a cascade, as shown in Rabii, was argued to be an obvious design choice.
    • Expectation of Success: The combination was presented as a straightforward integration of compatible and well-understood circuit elements, ensuring a high likelihood of success.

4. Key Claim Construction Positions

  • "inverting buffer" / "non-inverting buffer" (claim 2): Petitioner proposed that these terms be construed as circuits that isolate their output from their input and, when enabled, generate an output that is an inversion (or not an inversion) of the input. This construction was central to arguing that a single inverter qualifies as an "inverting buffer" and a cascade of two inverters qualifies as a "non-inverting buffer," as taught in Baker and Rabii.
  • "coupled for receiving": Petitioner clarified that this term does not require a direct physical connection or that the received signal be an exact replica of the source signal. This interpretation allows for intervening components, such as the inverting and non-inverting buffers, to be present between the boost signal source and the capacitors, which is critical for their obviousness arguments.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3 of Patent 6,127,875 as unpatentable.