PTAB

IPR2018-01000

Micron Technology v. North Star Innovations Inc

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: MULTI-STRAND SUBSTRATE FOR BALL-GRID ARRAY ASSEMBLIES AND METHOD
  • Brief Description: The ’743 patent describes a method for manufacturing ball-grid array (BGA) semiconductor packages. The method focuses on improving efficiency by processing multiple BGA substrates simultaneously on a single larger printed circuit board arranged in an N by M array, where both N and M are two or greater, before dividing them into individual packages.

3. Grounds for Unpatentability

Ground 1: Obviousness over Pastore, Altman, and Variot - Claims 1 and 8 are obvious over Pastore in view of Altman and Variot.

  • Prior Art Relied Upon: Pastore (Patent 5,285,352), Altman (WO 90/07792), and Variot (Patent 5,435,482).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Pastore taught the fundamental steps of assembling a BGA package on a printed circuit board substrate, including attaching a die, encapsulating it, and attaching solder balls. The key missing element, N x M array processing, was supplied by Altman, which disclosed manufacturing multiple "pad grid arrays" (a genus of which BGAs are a species) from a single 3x6 matrix substrate to improve efficiency. Variot was cited for teaching the importance of maintaining coplanarity in BGA packages, disclosing a planarity limit of approximately 0.15 mm to ensure electrical reliability, which Petitioner contended taught the "substantially planar" limitation of claim 1.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Pastore and Altman because both were Motorola-owned references directed to the same BGA technology (OMPAC), and it was known that using NxM array processing was more cost-effective. A POSITA would have incorporated Variot's teaching on planarity to ensure the resulting packages complied with industry standards (like the JEDEC standard referenced by Variot) and maintained reliable electrical connections.
    • Expectation of Success: Petitioner asserted a high expectation of success because Altman's array processing method was described as applicable to any suitable substrate, including the printed circuit board taught in Pastore. The combination was a straightforward application of a known manufacturing efficiency technique to a known product.

Ground 2: Obviousness over Houghten, Altman, and JEDEC - Claims 1, 5, 6, and 8 are obvious over Houghten in view of Altman, JEDEC Standard, and a POSA's knowledge.

  • Prior Art Relied Upon: Houghten ("New Package Takes on QFPs," Advanced Packaging, Winter 1993), Altman (WO 90/07792), and JEDEC Standard (No. MO-151A).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative primary reference, arguing that Houghten, another Motorola-related publication, also taught a complete method for assembling an OMPAC BGA. As in Ground 1, Altman was relied upon for its disclosure of manufacturing packages in an N x M array. The JEDEC Standard was used to teach the "substantially planar" limitation (disclosing a maximum coplanarity deviation of 0.15mm) and the specific substrate dimensions recited in dependent claims 5 (width on the order of 63 mm) and 6 (length of 187-212 mm). Petitioner argued these dimensions were the necessary substrate sizes for producing standard-sized BGAs in Altman's 3x6 array.
    • Motivation to Combine: The motivation asserted was that a POSITA would combine the teachings of Motorola-related BGA art (Houghten, Altman) to gain the known cost benefits of array processing. A POSITA would be expressly motivated to consult and apply the JEDEC Standard to ensure the manufactured BGAs were compliant with industry norms for size, I/O count, and planarity, making them compatible with other standard products.
    • Expectation of Success: Success was expected because Altman's process was applicable to Houghten's substrate, and the JEDEC Standard provided a predictable, finite set of standard dimensions. Petitioner argued that choosing a standard BGA body size to meet I/O requirements would directly dictate the required substrate dimensions for Altman's array, making the result a simple and predictable design choice.

Ground 3: Obviousness over Pastore, Altman, Variot, and Engelmaier - Claim 2 is obvious over Pastore in view of Altman, Variot, and Engelmaier.

  • Prior Art Relied Upon: Pastore (Patent 5,285,352), Altman (WO 90/07792), Variot (Patent 5,435,482), and Engelmaier ("Thermo-Mechanical Effects," 1989).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground built upon the combination from Ground 1 to address dependent claim 2. Engelmaier was introduced for its teaching on "tailoring" the coefficient of thermal expansion (CTE) of package components (substrate, die, and encapsulant) to be similar. This matching of CTEs was a known technique to reduce stress and warping during manufacturing, which Petitioner argued directly taught the limitation of using an encapsulant with a CTE "close to that of the semiconductor die and the printed circuit board."
    • Motivation to Combine: A POSITA, already motivated to combine Pastore, Altman, and Variot, would have been further motivated to apply Engelmaier's CTE tailoring technique to solve the known problem of warping and to improve the reliability of the final BGA packages.
    • Expectation of Success: The expectation of success was high because CTE values for common semiconductor manufacturing materials were well-known and listed in standard technical references, making it a routine matter for a POSITA to select materials with matching CTEs.

  • Additional Grounds: Petitioner asserted numerous additional obviousness challenges that built upon the core combinations of Pastore/Altman/Variot and Houghten/Altman/JEDEC. These grounds introduced further prior art references to teach specific, known modifications, including using stress-relief slots to prevent warping (adding Freyman, Patent 5,635,671), using specific substrate thicknesses to improve planarity (adding Lau, a 1993 IEEE publication), and adding an agent to the encapsulant for laser marking (adding Spanjer, Patent 4,753,863).

4. Key Claim Construction Positions

  • Petitioner argued that the term "substantially planar" should be construed in light of the prior art, specifically Variot and the JEDEC Standard. The petition contended that a POSA would understand this term to mean a specific, measurable planarity variation of less than approximately 0.15 mm. This construction was critical to Petitioner's argument that the prior art explicitly taught or suggested meeting this limitation to ensure package reliability and industry compatibility.

5. Key Technical Contentions (Beyond Claim Construction)

  • A central technical contention was that different BGA assembly techniques, specifically wire bonding and flip-chip, were known to be interchangeable in the art before the ’743 patent's filing date. This assertion was key to justifying the combination of references like Pastore (teaching wire bonding) with references like Altman (which discussed flip-chip embodiments), as a POSITA would have understood that the benefits of Altman's array processing were equally applicable to either assembly method.

6. Relief Requested

  • Petitioner requests institution of inter partes review and cancellation of claims 1-8 of the ’743 patent as unpatentable.