PTAB

IPR2018-01105

Intel Corp v. VLSI Technology LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Process for Forming an Electronic Device Including a Fin-Type Structure
  • Brief Description: The ’303 patent describes a method for manufacturing three-dimensional transistors (FinFETs). The process involves forming a semiconductor fin to a first height and then removing a portion of that fin to create a second, smaller height, thereby enabling the creation of transistors with different fin heights on the same substrate.

3. Grounds for Unpatentability

Ground 1: Anticipation by Yu - Claims 1-6, 8-11, and 18 are anticipated by Yu under 35 U.S.C. §102.

  • Prior Art Relied Upon: Yu (Application # 2005/0029603).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yu teaches every element of the challenged claims. Yu describes methods for manufacturing FinFET devices with varying fin aspect ratios to adjust their carrier mobility and achieve overall design goals. Critically, Yu explicitly discloses a process where “fin heights of different devices... may be selected by selectively masking some fins... and etching other exposed fins... to reduce their heights.” Petitioner contended this directly maps to the core limitation of the ’303 patent: forming a fin with a first height and then removing a portion to provide a second, smaller height. Yu’s disclosure of forming both NMOS and PMOS devices with different fin heights was argued to anticipate dependent claims directed to such structures.

Ground 2: Anticipation by Chau - Claims 1-7, 9-11, 13, 14, and 16 are anticipated by Chau under 35 U.S.C. §102.

  • Prior Art Relied Upon: Chau (Application # 2004/0036127).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Chau, which describes fabricating tri-gate transistors, also anticipates the claims. Chau’s method includes forming semiconductor fins on a substrate and then performing a thermal oxidation process to create a gate dielectric film on the fins. Petitioner argued that this thermal oxidation process inherently consumes a portion of the silicon fin, reacting with it to form silicon oxide. This consumption of the fin material constitutes the claimed step of "removing a portion of the first semiconductor fin" and results in a fin with a "second height... smaller than the first height." Because this oxidation can be performed on multiple fins simultaneously, Chau was argued to anticipate claims involving multiple fins and different channel regions.

Ground 3: Obviousness over Yu and Brask - Claim 7 is obvious over Yu in view of Brask under 35 U.S.C. §103.

  • Prior Art Relied Upon: Yu (Application # 2005/0029603) and Brask (Application # 2005/0148137).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that claim 7, which depends from claim 2, adds the limitation of forming a first fin from an n-doped semiconductor region and a second fin from a p-doped region. While Yu teaches the fundamental process of varying fin heights, it does not explicitly detail the initial doping of the semiconductor layer from which fins are formed. Brask, however, was shown to remedy this by describing the fabrication of tri-gate transistors where n-type and p-type fins are formed from distinct n-type and p-type regions of a semiconductor film.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the teachings of Yu and Brask to facilitate the creation of high-performance CMOS circuits. Both references address the formation of non-planar transistors (FinFETs/tri-gate transistors) and their use in CMOS devices, which require both n-type (NMOS) and p-type (PMOS) transistors. A POSITA would have found it logical to apply Brask’s explicit teaching of forming differently doped fins to Yu’s method for varying fin heights to optimize the performance of these complementary devices.
    • Expectation of Success: The combination was presented as a predictable application of a known technique (forming fins from doped regions) to a known process (varying fin height by etching) to achieve a desired, predictable result (optimized CMOS FinFETs).

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 2, 5, 8, 11, and 15 over the combination of Chau and Yu, relying on similar motivations to combine Chau’s base process with Yu’s explicit teachings on varying fin heights to achieve desired carrier mobilities.

4. Key Claim Construction Positions

  • "height": Petitioner argued that this term, central to independent claims 1 and 18, should be construed according to its express definition in the ’303 patent’s specification. The patent defines "height" as the "physical dimension of distance from the base to the top of a structure in a direction substantially perpendicular to the primary surface." This construction was crucial to Petitioner’s argument that processes like thermal oxidation (in Chau) or etching (in Yu), which reduce this physical dimension, meet the claim limitation of "removing a portion" to change the fin's height.

5. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 1-11, 13-16, and 18 of the ’303 patent as unpatentable.