PTAB

IPR2018-01155

Intel Corporation v. Godo Kaisha IP Bridge 1

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1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device and Method for Manufacturing the Same
  • Brief Description: The ’900 patent relates to a semiconductor device design intended to mitigate the "optical proximity effect," a known distortion issue in photolithography. The invention discloses a transistor structure featuring a gate conductor film with a substantially constant dimension in the gate length direction, combined with a gate contact that is wider than the gate film, to prevent undesirable rounding and dimensional variations during fabrication.

3. Grounds for Unpatentability

Ground I: Obviousness over Maeda and Wieczorek - Claims 1-4 and 10 are obvious over Maeda in view of Wieczorek.

  • Prior Art Relied Upon: Maeda (Japanese Unexamined Patent Appl. Pub. S62-217635) and Wieczorek (Patent 6,566,718).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Maeda discloses the core features of independent claim 1, including a semiconductor device with a linear gate electrode (gate electrode 6) and an oversized contact (contact hole 13) designed to prevent etching problems from mask misalignment. This structure includes a gate conductor with a constant dimension that extends over an active region and an isolation region, and a contact larger than the gate connected over the isolation region. Petitioner cited Wieczorek as teaching standard, well-known elements to supplement Maeda, such as ensuring the element isolation region fully surrounds the active regions and adding sidewall spacers (for claim 10).
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings because transistor isolation is a fundamental design requirement, and both references address similar layout challenges with linear gates and oversized contacts. Petitioner asserted a POSITA would look to Wieczorek for conventional methods of implementing isolation and sidewalls in a structure like Maeda's to improve device performance, increase efficiency, and enable further miniaturization.
    • Expectation of Success: Petitioner contended that success would be expected because the combination involved applying predictable and standard semiconductor design techniques (complete isolation, sidewall spacers) to a conventional transistor layout.

Ground II: Obviousness over Maeda, Wieczorek, and Gheewalla - Claims 5-9 are obvious over Maeda, Wieczorek, and Gheewalla.

  • Prior Art Relied Upon: Maeda (Japanese Unexamined Patent Appl. Pub. S62-217635), Wieczorek (Patent 6,566,718), and Gheewalla (Patent 5,723,883).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the combination in Ground I to address claims 5-9, which are directed to a complementary metal-oxide-semiconductor (CMOS) structure containing both N-type and P-type transistors. Petitioner argued that while Maeda discloses paired NMOS (N-type) transistors, Gheewalla explicitly teaches arranging NMOS and PMOS (P-type) transistors together in a CMOS layout to achieve known benefits. The argument was that modifying Maeda's paired NMOS design into a CMOS design by replacing one N-type transistor with a P-type transistor, as taught by Gheewalla, was a routine and obvious modification for a POSITA.
    • Motivation to Combine: The primary motivation was to achieve the well-known advantages of CMOS technology, particularly lower power consumption, which was the industry standard at the time of the invention. As all three references relate to MOS transistors and utilize similar linear layouts, Petitioner argued their teachings would be readily combined to create an improved, power-efficient device.
    • Expectation of Success: Petitioner asserted a high expectation of success, as converting an NMOS transistor to a PMOS transistor was a routine design choice that involved predictable changes to dopants without altering the fundamental device structure taught by Maeda.

Ground III: Obviousness over Chakihara - Claims 1-4 are obvious over Chakihara.

  • Prior Art Relied Upon: Chakihara (Patent 7,190,031).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Chakihara alone renders claims 1-4 obvious. Chakihara is directed to scaling down memory devices and explicitly addresses fabrication issues caused by "interference of the exposure light," the same problem targeted by the ’900 patent. Petitioner argued that Chakihara discloses every element of independent claim 1, including island-shaped active regions surrounded by isolation trenches, a gate conductor film (gate electrode 7B) with a constant dimension, and a larger gate contact (contact hole 22) formed over the isolation region. This structure is used to ensure the gate electrodes "can be patterned with satisfactory accuracy." Petitioner mapped the limitations of dependent claims 2-4 directly to features disclosed in Chakihara.
    • Motivation to Combine: Not applicable, as this is a single-reference ground under 35 U.S.C. §103.

4. Relief Requested

  • Petitioner requests institution of inter partes review and cancellation of claims 1-10 of Patent 7,709,900 as unpatentable.