PTAB

IPR2018-01263

Samsung Electronics Co Ltd v. Tessera Advanced Technologies Inc

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1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device And Method For Producing The Same
  • Brief Description: The ’298 patent relates to semiconductor chip-scale package (CSP) technology. The invention discloses a device structure intended to enable high-speed signal transmission by creating distinct pathways for "high-speed signals" and "regular signals," where the high-speed path minimizes electrical resistance and delay by forming an external electrode directly above its corresponding element electrode, thereby eliminating a longer connecting wire that is used for the regular signal path.

3. Grounds for Unpatentability

Ground 1: Obviousness over Yanagida and Mutter - Claims 1-4 and 8-13 are obvious over Yanagida in view of Mutter.

  • Prior Art Relied Upon: Yanagida (Patent 5,918,144) and Mutter (Patent 3,461,357).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yanagida taught a semiconductor device for high-speed operation with a structure nearly identical to that claimed in the ’298 patent. Specifically, Yanagida disclosed a multilevel interconnect structure with separate electrodes for high-speed signals (where a solder ball is formed directly above an electrode pad) and for regular-speed signals (where a solder ball is offset from its electrode pad and connected via a Ball Limiting Metal (BLM) film acting as a wire). Petitioner contended that the only limitation not explicitly disclosed by Yanagida was the connection of both the high-speed and regular-speed element electrodes to the same underlying semiconductor element.
    • Motivation to Combine: Petitioner asserted that Mutter disclosed what was, at the time, a common and well-known arrangement of connecting two separate electrodes—one for high-speed data signals and another for regular-speed power signals—to a single transistor. A POSITA seeking to implement Yanagida’s high-speed device would have been motivated to apply Mutter’s conventional transistor connection scheme to connect Yanagida’s high-speed and regular-speed electrodes to the same semiconductor element, as this was a fundamental design choice for creating functional I/O circuits.
    • Expectation of Success: A POSITA would have had a high expectation of success, as the combination merely involved applying a known and established electrode connection technique (from Mutter) to a similar multilevel semiconductor device structure (from Yanagida) to achieve a predictable and functional result.

Ground 2: Obviousness over Yanagida and Maitani - Claims 1-4 and 8-13 are obvious over Yanagida in view of Maitani.

  • Prior Art Relied Upon: Yanagida (Patent 5,918,144) and Maitani (WO 00/44043).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground presented an alternative to Ground 1, again relying on Yanagida to teach the core structure of the challenged claims, including the distinct high-speed (direct) and regular-speed (offset wire) electrode configurations.
    • Motivation to Combine: Petitioner argued that Maitani, like Mutter, taught the conventional practice of connecting two different types of wiring—"signal wiring" and "power wiring"—to a single transistor within a CSP. A POSITA would combine this teaching from Maitani with Yanagida's device to connect Yanagida’s corresponding high-speed (signal) and regular-speed (power) electrodes to a single semiconductor element to achieve high-speed operation. Petitioner also asserted a secondary motivation: a POSITA would look to Maitani to improve upon Yanagida's method for film adhesion, as Maitani taught a superior heat treatment process.
    • Expectation of Success: Given that both references operate in the same field of high-density CSPs and the combination relies on applying fundamental principles of transistor interconnection, a POSITA would have expected the combination to yield a predictable improvement in device functionality and reliability.

  • Additional Grounds: Petitioner asserted two additional obviousness challenges (Ground 2 and Ground 4) targeting claims 5 and 6. These grounds added Berglund (Patent 4,698,128) to the primary combinations of Yanagida/Mutter and Yanagida/Maitani, respectively. The motivation to include Berglund was to teach the claimed limitation of forming openings with sloped walls (i.e., an inclination of less than 90°), which Berglund taught was a known and desirable technique to ensure adequate step coverage of conductive layers deposited into the openings.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-6 and 8-13 of the ’298 patent as unpatentable.