PTAB

IPR2018-01264

Samsung Electronics Co., Ltd. v. Tessera Advanced Technologies, Inc.

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1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device And Method For Producing The Same
  • Brief Description: The ’616 patent discloses a method for manufacturing a semiconductor device, specifically a chip-scale package (CSP), that purports to allow for high-speed signal transmission. The method involves a specific multi-step process for forming external electrodes directly above element electrodes to reduce resistance and signal delay.

3. Grounds for Unpatentability

Ground 1: Claims 1-4 and 8-9 are obvious over Yanagida in view of Maitani.

  • Prior Art Relied Upon: Yanagida (Patent 5,918,144) and Maitani (WO 00/44043).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yanagida taught most steps of independent claim 1, including forming element electrodes on a substrate, covering them with a patterned insulating layer, and creating openings to the electrodes. However, Yanagida allegedly failed to explicitly teach the claimed three-step process for forming the external electrodes: (1) depositing a first, thin, substantially continuous conductive film; (2) selectively forming a second, thick conductive film on the first film; and (3) removing portions of the first thin film not covered by the second thick film. Petitioner asserted that Maitani taught this exact electroplating process. Maitani disclosed sputtering a thin continuous "power supply layer" as a seed layer, selectively electroplating a much thicker copper wire onto it, and then using the thick copper wire as a mask to etch away the exposed portions of the underlying seed layer.
    • Motivation to Combine: A POSITA would combine the references because both address the manufacture of high-density, high-speed CSPs. Maitani’s electroplating method was a known and advantageous alternative to Yanagida’s sputtering/lift-off process, as it was faster, less expensive, and enabled the formation of significantly thicker conductive films. A thicker film provides lower electrical resistance, which directly improves device speed and reliability—the express goals of Yanagida.
    • Expectation of Success: A POSITA would have had a high expectation of success, as combining these well-understood fabrication techniques to improve a semiconductor device's performance was a predictable application of existing art.

Ground 2: Claims 5 and 6 are obvious over Yanagida in view of Maitani and Berglund.

  • Prior Art Relied Upon: Yanagida (Patent 5,918,144), Maitani (WO 00/44043), and Berglund (Patent 4,698,128).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground 1 and additionally addressed dependent claims 5 and 6, which require the openings in the insulating layer to have sloped wall surfaces with an inclination of less than 90 degrees. Petitioner contended that Berglund explicitly taught the design and desirability of forming via holes with sloped or tapered profiles to ensure adequate "step coverage" of the conductive layer subsequently deposited into the hole. Petitioner also argued that Maitani inherently disclosed sloped walls as a natural result of its described photosensitive polyimide development and curing process.
    • Motivation to Combine (for Berglund): A POSITA would combine Berglund with the Yanagida/Maitani combination to solve the well-known problem of poor step coverage in non-sloped vias. Berglund provided a known solution to a known problem in semiconductor fabrication, making it an obvious modification to improve the structural integrity and reliability of the resulting device.
    • Expectation of Success: Incorporating sloped via walls as taught by Berglund was a standard and predictable process modification in the field of semiconductor manufacturing to enhance yield and performance.

Ground 3: Claims 1-4 and 8-9 are obvious over Yanagida in view of Tokushige.

  • Prior Art Relied Upon: Yanagida (Patent 5,918,144) and Tokushige (Japanese Application 2000-195862).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground presented an alternative to Ground 1, arguing that Tokushige, like Maitani, supplied the teachings for the multi-step electrode formation process allegedly missing from Yanagida. Petitioner asserted that Tokushige taught a directly analogous electroplating method: sputtering a continuous thin copper film layer to act as a plating electrode, applying a photoresist, selectively electroplating a thicker wiring layer in the unmasked areas, and then using the thick wiring layer as a mask to etch away the now-uncovered portions of the thin film. Tokushige also explicitly taught connecting the electrodes to an underlying MOS transistor.
    • Motivation to Combine: The motivation was similar to that for combining Yanagida with Maitani. A POSITA would combine Yanagida with Tokushige because both relate to improving the reliability of CSPs. Tokushige’s electroplating method offered the same benefits of creating a thicker, lower-resistance conductive film (2-5µm vs. Yanagida's 1µm) to achieve Yanagida's stated goals of high-speed operation and improved reliability.
    • Expectation of Success: Applying Tokushige’s well-understood electroplating process to Yanagida’s base structure would have been a predictable and successful integration of known technologies to achieve a known benefit.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) against claims 5 and 6 based on the combination of Yanagida, Tokushige, and Berglund, relying on similar design modification theories as presented in the grounds above.

4. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-6 and 8-9 of the ’616 patent as unpatentable.