PTAB

IPR2018-01264

Samsung Electronics Co Ltd v. Tessera Advanced Technologies Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device And Method For Producing The Same
  • Brief Description: The ’616 patent describes a method for manufacturing a "chip-scale package" (CSP) semiconductor device. The method purports to enable high-speed signal transmission by forming a first external electrode directly above a first element electrode, in contrast to conventional methods that used longer connecting wires, which introduced signal delay.

3. Grounds for Unpatentability

Ground 1: Obviousness over Yanagida and Maitani - Claims 1-4 and 8-9 are obvious over Yanagida in view of Maitani.

  • Prior Art Relied Upon: Yanagida (Patent 5,918,144) and Maitani (WO 00/44043).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yanagida taught a method for manufacturing a high-speed semiconductor device that disclosed nearly all the claimed steps in the same order. However, Yanagida did not explicitly disclose connecting the "element electrodes" to a semiconductor element or the specific three-step process for forming the external electrodes recited in the ’616 patent (i.e., forming a thin continuous film, selectively forming a thick film on top, and then patterning both films). Petitioner asserted Maitani supplied these missing elements, as it disclosed a similar CSP manufacturing process that used an electroplating method to selectively form a thick conductive wire over a thin continuous conductive layer, which was then used as a mask to etch the underlying thin layer. Maitani also explicitly taught connecting electrodes to semiconductor elements (MISFETs) via signal and power wiring.
    • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would combine Yanagida and Maitani because both addressed the same technical problem of creating high-density, high-speed CSPs. A POSITA would have been motivated to replace Yanagida’s sputtering process with Maitani’s electroplating process to achieve several known benefits, including the ability to form a thicker conductive layer. This thicker layer would reduce electrical resistance (improving device speed) and function as a better anti-diffusion layer, thereby achieving Yanagida’s own stated goals more effectively.
    • Expectation of Success: A POSITA would have expected success in this combination because it involved applying a known, advantageous fabrication technique (electroplating from Maitani) to a similar system (the CSP structure of Yanagida) to achieve the predictable result of improved electrical performance and reliability.

Ground 2: Obviousness over Yanagida, Maitani, and Berglund - Claims 5 and 6 are obvious over Yanagida in view of Maitani and further in view of Berglund.

  • Prior Art Relied Upon: Yanagida (Patent 5,918,144), Maitani (WO 00/44043), and Berglund (Patent 4,698,128).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Yanagida and Maitani to address the additional limitations of claims 5 and 6, which required the openings in the insulating layer to have sloped wall surfaces (inclined at less than 90°). Petitioner argued that while Maitani’s figures depicted such sloped walls, Berglund explicitly taught the reason for and methods of creating them. Berglund explained that forming sloped or tapered profiles for contact holes (vias) was a known technique necessary to ensure "adequate step coverage" of the conductive layer subsequently deposited into the hole.
    • Motivation to Combine: Petitioner asserted that a POSITA implementing the process of Yanagida and Maitani would have recognized the well-known problem of ensuring good metal coverage in vias. Berglund directly addressed this problem and provided the known solution of forming sloped contacts. Therefore, a POSITA would have been motivated to incorporate Berglund’s teachings to improve the reliability and yield of the manufacturing process.
    • Expectation of Success: The outcome was predictable, as creating sloped via walls was a standard method for improving step coverage in semiconductor fabrication.

Ground 3: Obviousness over Yanagida and Tokushige - Claims 1-4 and 8-9 are obvious over Yanagida in view of Tokushige.

  • Prior Art Relied Upon: Yanagida (Patent 5,918,144) and Tokushige (Japanese Application Publication 2000-195862).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative to Ground 1, using Tokushige instead of Maitani to supplement Yanagida. Petitioner argued that Tokushige, like Maitani, disclosed the elements missing from Yanagida. Specifically, Tokushige taught a preferred electroplating method that involved sputtering a continuous thin copper film, selectively electroplating a thicker wiring layer on top, and then using the thicker layer as a mask to remove the uncovered portions of the thin film. Tokushige also disclosed connecting an aluminum electrode to the drain electrode of a MOS transistor.
    • Motivation to Combine: The motivation was analogous to that for combining Yanagida and Maitani. Both Yanagida and Tokushige aimed to improve the reliability of CSPs. A POSITA would have been motivated to apply Tokushige's more advanced electroplating method to Yanagida's structure to form a thicker conductive film, thereby reducing resistance and improving performance in line with Yanagida’s goals.
    • Expectation of Success: A POSITA would have reasonably expected that substituting one known metal deposition and patterning technique (Tokushige's electroplating) for another (Yanagida's sputtering) would yield a predictable improvement in device performance.
  • Additional Grounds: Petitioner asserted that claims 5 and 6 are obvious over Yanagida in view of Tokushige and Berglund, relying on a similar rationale as Ground 2 for incorporating Berglund’s teachings on sloped via walls.

4. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-6 and 8-9 of the ’616 patent as unpatentable.