PTAB

IPR2018-01293

Intel Corp v. Qualcomm Inc

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1. Case Identification

2. Patent Overview

  • Title: Processor Communication Using a Trigger Protocol
  • Brief Description: The ’490 patent discloses a mobile terminal with a modem processor and an application processor that communicate over an interconnectivity bus. The technology aims to conserve power by reducing the number of times the bus must transition from a low-power state to an active state by consolidating data transfers into a single active period, using a "trigger" protocol to coordinate uplink and downlink transmissions.

3. Grounds for Unpatentability

Ground 1: Claims 1, 4, 5, 6, and 8 are obvious over Heinrich in view of Balasubramanian.

  • Prior Art Relied Upon: Heinrich (Patent 9,329,671) and Balasubramanian (Patent 8,160,000).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Heinrich taught a mobile device with the core components of claim 1: a modem processor (baseband processor), an application processor, and an interconnectivity bus. Heinrich also disclosed using a timer ("lazy timer") to buffer and hold data at the modem processor for aggregated transmission to the application processor, thus saving power by reducing bus transitions. However, Petitioner contended that Heinrich did not explicitly teach the claimed "trigger" mechanism, where the application processor's transmission is initiated by the receipt of data from the modem processor. Petitioner asserted that Balasubramanian supplied this missing element by disclosing a system where a network interface is triggered to send its queued downlink packets upon receiving uplink packets from a transceiver, all within a single wake state to conserve power.
    • Motivation to Combine: A POSA would combine Heinrich and Balasubramanian because both references address the same problem—power consumption from bus state transitions in multi-processor systems—using analogous solutions of buffering and aggregating data. Heinrich taught the benefit of sending data when the destination processor is already awake. Balasubramanian provided a known, specific technique (the trigger mechanism) to implement this principle. Therefore, a POSA would have been motivated to substitute Balasubramanian’s efficient trigger scheme into Heinrich’s similar system to predictably improve power savings.
    • Expectation of Success: A POSA would have had a reasonable expectation of success in the combination. Balasubramanian's trigger scheme was argued to be just a specific implementation of the broader principle taught in Heinrich—determining that the other processor is awake before initiating a data transfer. Incorporating this known technique for a known purpose (power saving) into a similar system would have yielded the expected result of fewer bus transitions.

Ground 2: Claims 2 and 3 are obvious over the combination of Heinrich and Balasubramanian in view of Tsai.

  • Prior Art Relied Upon: Heinrich (Patent 9,329,671), Balasubramanian (Patent 8,160,000), and Tsai (Patent 8,112,646).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground 1 to address dependent claims 2 and 3, which further require the interconnectivity bus to be a Peripheral Component Interconnect (PCI) compliant bus (claim 2) and a PCI Express (PCIe) bus (claim 3). While the Heinrich/Balasubramanian combination disclosed a generic bus, Petitioner argued that Tsai expressly taught the use of a PCI and PCIe bus to connect a communications sub-system (baseband processor) and a computing sub-system (application processor).
    • Motivation to Combine: A POSA would have been motivated to incorporate Tsai’s teaching because PCIe was a well-known, widely adopted, general-purpose bus standard for chip-to-chip communication in mobile devices at the time of the invention. Heinrich itself taught that its system could use various industry-standard buses. Modifying the combined Heinrich/Balasubramanian system to use a popular and high-performance bus like PCIe, as taught by Tsai, would have been an obvious and predictable design choice to improve performance and ensure compatibility.
    • Expectation of Success: Both Heinrich and Tsai disclosed that their respective systems could use several different, interchangeable bus types (e.g., USB, PCI, PCIe). Because these buses were known to be suitable for connecting baseband and application processors, a POSA would have reasonably expected that substituting the PCIe bus from Tsai into the system of Heinrich would work for its intended purpose without issue.

4. Key Claim Construction Positions

  • Petitioner argued that the term "triggered by", which was added during prosecution to achieve allowance, should be construed as "initiated in response to". This construction was central to Petitioner's obviousness argument, as it contended that the prior art did not need to use the exact word "trigger." Instead, Petitioner argued that Balasubramanian's disclosure—where the receipt of data from a first processor causes a second processor to send its own data—met the "initiated in response to" standard, thereby teaching the claimed limitation.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-6 and 8 of Patent 9,535,490 as unpatentable under 35 U.S.C. §103.