PTAB

IPR2018-01295

Intel Corporation v. Qualcomm Incorporated

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1. Case Identification

2. Patent Overview

  • Title: Method of Controlling Power Consumption in a Computing Device
  • Brief Description: The ’490 patent discloses a method for conserving power in computing devices, such as mobile terminals, that contain both a modem processor and an application processor. The claimed invention seeks to reduce power consumption by minimizing transitions of the interconnectivity bus between low-power and active states. This is achieved by consolidating data traffic: the receipt of data from the modem processor (downlink) is used as a "trigger" to cause the immediate transmission of any buffered data from the application processor (uplink) within the same single active period of the bus.

3. Grounds for Unpatentability

Ground 1: Obviousness over Heinrich and Balasubramanian - Claims 16, 22-24 are obvious over Heinrich in view of Balasubramanian.

  • Prior Art Relied Upon: Heinrich (Patent 9,329,671) and Balasubramanian (Patent 8,160,000).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Heinrich discloses most elements of the independent claims, including a computing device with a modem processor (baseband processor) and an application processor communicating over a bus. Heinrich teaches buffering data and using "lazy timers" (corresponding to the claimed "uplink timer" and "downlink timer") to delay transmissions and group them to save power. However, Heinrich primarily relies on timer expiration to send data. Petitioner asserted that Balasubramanian supplies the crucial "trigger" limitation. Balasubramanian discloses a power-saving system where the receipt of an uplink packet at a network interface triggers the interface to transmit its queued downlink packets during the same single wake state. Petitioner contended this maps directly to the ’490 patent’s core limitation of using data receipt to trigger a responsive data transmission before the bus returns to a low-power state.
    • Motivation to Combine: A POSITA would combine Heinrich and Balasubramanian because both references are in the same technical field (processor-to-processor communications) and address the identical problem of reducing power consumption from state transitions. Petitioner argued that Heinrich is open to modification, as it discusses finding the "best possible time to trigger" transmissions. Balasubramanian provides a known, predictable, and highly efficient solution—the trigger mechanism—to improve upon Heinrich's timer-based system. Combining the two would allow for opportunistically using an already-active bus, a known method for achieving greater power savings.
    • Expectation of Success: Petitioner asserted a POSA would have had a reasonable expectation of success in this combination. Balasubramanian's trigger is simply another method for determining that the receiving processor and bus are "awake," a concept already contemplated by Heinrich’s scheduler. Therefore, incorporating this known trigger technique from Balasubramanian into Heinrich’s system to further optimize power consumption would be a straightforward and predictable design modification.

Ground 2: Obviousness over Heinrich, Balasubramanian, and Tsai - Claim 17 is obvious over the combination of Heinrich and Balasubramanian in view of Tsai.

  • Prior Art Relied Upon: Heinrich (Patent 9,329,671), Balasubramanian (Patent 8,160,000), and Tsai (Patent 8,112,646).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that claim 17, which depends from claim 16, adds the limitation that the data is passed over a "peripheral component interface (PCI) compliant bus." While the primary combination of Heinrich and Balasubramanian teaches the method of claim 16, it does not explicitly disclose a PCI bus. Petitioner asserted that Tsai fills this gap by teaching a system with a baseband processor and an application processor connected by a bus, explicitly listing PCI and PCI Express (PCIe) as suitable bus protocols.
    • Motivation to Combine: A POSITA would be motivated to look to Tsai to implement the interconnectivity bus for the Heinrich/Balasubramanian system. All three references concern power management in processor-to-processor communications. At the time of the invention, PCIe was a "general-purpose interconnect of choice" for chip-to-chip communications. It would have been an obvious design choice to select a standard, widely adopted bus like the PCI/PCIe bus taught by Tsai for the system disclosed in the primary combination.
    • Expectation of Success: Petitioner contended that success would be highly predictable. Heinrich already discloses the use of other standard bus interfaces, such as USB. Tsai teaches that bus types like USB, PCI, and PCIe are interchangeable options for the same purpose. A POSA would understand that substituting one standard, serial, packet-based bus for another is a routine engineering task with a high likelihood of success, as they share many fundamental similarities.

4. Key Claim Construction Positions

  • Petitioner dedicated a section to construing the claim phrase "triggered by" / "triggers" to mean "initiated in response to". This construction was presented as crucial to the invalidity argument. Petitioner argued this meaning is supported by the ’490 patent’s specification, its prosecution history, and plain dictionary definitions. The construction was used to distinguish the claimed invention from prior art that relied merely on pre-set timers (which are not "responsive to" an event like data receipt), a distinction that was key to overcoming an Examiner rejection during the original prosecution.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 16-17 and 22-24 of Patent 9,535,490 as unpatentable under 35 U.S.C. §103.