PTAB

IPR2018-01295

Intel Corp v. Qualcomm Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Controlling Power Consumption in a Computing Device
  • Brief Description: The ’490 patent discloses systems and methods for conserving power in a computing device, such as a mobile terminal, containing a modem processor and an application processor. The invention focuses on reducing the number of power state transitions of an interconnectivity bus by coordinating the transmission of buffered downlink and uplink data into a single active period for the bus.

3. Grounds for Unpatentability

Ground 1: Obviousness over Heinrich in view of Balasubramanian - Claims 16, 22-24 are obvious over Heinrich in view of Balasubramanian

  • Prior Art Relied Upon: Heinrich (Patent 9,329,671) and Balasubramanian (Patent 8,160,000).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Heinrich disclosed the core architecture of the challenged claims: a computing device with a baseband (modem) processor and an application processor that communicate over a bus. Heinrich taught buffering data on both processors and using timers ("lazy timers") to delay and aggregate data transmissions, thereby reducing power consumption by minimizing the number of times the processors and bus transition from a sleep state to an active state. However, Petitioner contended that Heinrich did not explicitly teach using the receipt of data from the modem as a "trigger" for the application processor to send its own buffered data. Petitioner asserted that Balasubramanian supplied this missing element. Balasubramanian disclosed a power-saving system where two processing nodes exchange data, and crucially, taught that the receipt of an uplink packet at a second node can act as a "trigger" to transmit any queued downlink packets back to the first node during the same single "wake state." Petitioner argued that combining Balasubramanian's trigger mechanism with Heinrich's timer-based buffering system rendered the challenged claims obvious.
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine Heinrich and Balasubramanian for several reasons. Both references addressed the same problem in the same field: reducing power consumption in processor-to-processor communications by minimizing state transitions. A POSITA seeking to optimize Heinrich's power-saving scheme would have looked to analogous systems like Balasubramanian. Furthermore, Heinrich recognized the benefit of sending data only when the receiving processor is already awake. Balasubramanian’s trigger mechanism provided an efficient and known method to achieve this, as the receipt of data inherently confirms the receiving processor is active and able to accept a return transmission.
    • Expectation of Success: Petitioner asserted a POSITA would have a reasonable expectation of success. Heinrich disclosed various techniques for determining when a processor is awake to trigger data transmission. Balasubramanian's method—using the receipt of data as that trigger—was simply another known, predictable way to make this determination. Integrating this known trigger technique into Heinrich's system to achieve the expected result of fewer bus transitions would have been a straightforward design choice.

Ground 2: Obviousness over Heinrich, Balasubramanian, and Tsai - Claim 17 is obvious over the combination of Heinrich and Balasubramanian in view of Tsai

  • Prior Art Relied Upon: Heinrich (Patent 9,329,671), Balasubramanian (Patent 8,160,000), and Tsai (Patent 8,112,646).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued this combination rendered dependent claim 17 obvious. Claim 17 added the limitation that the data is passed over a "peripheral component interface (PCI) compliant bus." While the primary combination of Heinrich and Balasubramanian disclosed various industry-standard buses (e.g., USB), neither explicitly mentioned a PCI bus. Petitioner asserted that Tsai disclosed this specific limitation. Tsai described a power management system connecting a communications sub-system (with a baseband processor) and a computing sub-system (with an application processor) via a bus, and explicitly identified PCI and PCI Express (PCIe) as suitable bus protocols.
    • Motivation to Combine: Petitioner argued a POSITA would have been motivated to use the PCI/PCIe bus from Tsai to implement the system in Heinrich. All three references were directed to the same technology (processor-to-processor communications) and the same goal (power savings). By the time of the ’490 patent’s invention, PCIe had become a widely adopted, general-purpose interconnect for chip-to-chip communications. It would have been a natural and obvious choice for a POSITA implementing Heinrich's system to select the common and effective PCI/PCIe bus taught by Tsai.
    • Expectation of Success: Petitioner contended that success would be expected because both Heinrich and Tsai taught that different standard buses, including USB and PCIe, could be used interchangeably to connect processors. Given the similarities and standardized nature of these packet-based serial buses, a POSITA would reasonably expect that using a PCI-compliant bus from Tsai within the Heinrich architecture would function as intended without requiring undue experimentation.

4. Key Claim Construction Positions

  • Petitioner argued that the key claim term "triggered by" / "triggers" should be construed to mean "initiated in response to." This construction was critical because the Patent Owner added the "trigger" limitation during prosecution to overcome prior art. Petitioner asserted its proposed construction was supported by the patent's specification, claims, and prosecution history. Under this construction, Petitioner argued that Balasubramanian's disclosure—where the receipt of a packet from a first processor causes a second processor to transmit its own queued packets—squarely met the "trigger" limitation of the claims.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 16-17 and 22-24 of the ’490 patent as unpatentable under 35 U.S.C. §103.