PTAB

IPR2018-01316

Apple Inc v. Qualcomm Inc

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: MULTIPLE SUPPLY-VOLTAGE POWER-UP/DOWN DETECTORS
  • Brief Description: The ’674 patent describes a power-on/off-control (POC) network for devices with multiple supply voltages, such as a lower-voltage core network and a higher-voltage I/O network. The invention aims to prevent erroneous signals during power transitions by using a power-up/down detector with a feedback network that allegedly improves sensitivity and reduces leakage current.

3. Grounds for Unpatentability

Ground 1: Obviousness over Steinacker, Doyle, and Park - Claims 8-9, 12-13, and 16-22 are obvious over Steinacker in view of Doyle and Park.

  • Prior Art Relied Upon: Steinacker (Patent 7,279,943), Doyle (Patent 4,717,836), and Park (a 2006 IEEE publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Steinacker taught a circuit arrangement with multiple voltage domains and a voltage level detector to manage power states, addressing the same problem as the ’674 patent, but only broadly suggested using an inverter. Doyle was argued to disclose a specific, improved CMOS inverter with a feedback network to provide a stable trip point. Park was cited for teaching the "forced stack technique"—replacing a single transistor with two stacked transistors—as a known method to reduce leakage current in CMOS circuits. Petitioner contended the combination of Steinacker’s overall architecture with Doyle’s specific inverter and Park’s leakage reduction technique discloses the claimed POC network, including its power detector (comprising stacked transistors per Park), signal processor (Doyle's inverter), and feedback elements (Doyle's feedback transistor).
    • Motivation to Combine: A POSITA would combine Steinacker with Doyle as a simple substitution of a known, improved inverter (Doyle) for the generic one suggested by Steinacker to achieve predictable stability. A POSITA would further modify the resulting circuit with Park's technique to achieve the well-known goal of reducing leakage power, a common design consideration for CMOS inverters.
    • Expectation of Success: Petitioner argued success was expected because the combination involved applying known solutions (an improved inverter, a leakage-reduction technique) to their known problems, yielding only predictable results.

Ground 2: Obviousness over Admitted Prior Art and Majcherczak - Claims 8-9, 12-13, and 17-21 are obvious over AAPA in view of Majcherczak.

  • Prior Art Relied Upon: Applicant's Admitted Prior Art (AAPA) (disclosed in the ’674 patent) and Majcherczak (Application # 2002/0163364).

  • Core Argument for this Ground:

    • Prior Art Mapping: The AAPA was described as a standard POC system that included a power-up/down detector but lacked the claimed feedback network. Majcherczak was asserted to teach a voltage detection device for the same purpose that explicitly included a feedback transistor (M6) connected to provide hysteresis, thereby stabilizing the circuit. Petitioner argued that adding Majcherczak's feedback transistor to the AAPA's base circuit would result in a POC network having all the features of independent claims 8 and 17, including a means for decreasing and increasing the current capacity of the detector, as the feedback transistor modulates current flow through the main pull-up transistor.
    • Motivation to Combine: A POSITA would be motivated to integrate the feedback transistor from Majcherczak into the AAPA system to gain the known benefit of "proper stabilizing" and hysteresis. Both references address the same problem in multi-voltage systems, making the combination a logical step to improve the performance of the base AAPA circuit.
    • Expectation of Success: Petitioner claimed a reasonable expectation of success because the two systems shared many functionally commensurate elements and the proposed modification was merely the application of a known technique (adding a feedback transistor for hysteresis) to a similar device to achieve its expected purpose.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 2b) for claims 16 and 22 based on the combination of AAPA and Majcherczak, further in view of Matthews (Patent 6,646,844), to teach the application of the claimed device in specific electronic products such as mobile phones and computers.

4. Key Claim Construction Positions

  • "signal processor" (claims 8, 17): Petitioner argued that while the term is not explicitly defined, the specification’s only embodiment (FIGS. 4-6) describes the signal processor as an inverting amplifier. Therefore, the term should be construed to at least encompass an amplifying inverter, allowing prior art inverters from Doyle and Majcherczak to satisfy the limitation.
  • Means-Plus-Function Terms (claims 17-20): Petitioner identified several "means for" limitations and proposed corresponding structures from the ’674 patent's specification pursuant to §112, ¶ 6. Key examples included construing "means for detecting a power-on" as the power up/down detector (e.g., detector 306) and "means...for decreasing a current capacity" as the feedback network (e.g., network 310). These constructions were central to mapping the structurally equivalent components from the prior art combinations onto the claim limitations.

5. Key Technical Contentions (Beyond Claim Construction)

  • Application of Transistor Stacking: A central technical argument was that a POSITA would have found it obvious to apply Park's "forced stack technique" to the transistors within Doyle's inverter. Petitioner contended this was not an inventive step but a routine, predictable design modification used in the art to reduce leakage current in standard CMOS components.
  • Equivalence of Feedback Networks: Petitioner asserted that the feedback transistor (M6) from Majcherczak, when integrated into the AAPA circuit, is structurally and functionally equivalent to the claimed feedback network (transistor M8). It was argued that both are connected in parallel with a pull-up transistor and operate in the same way (via a feedback signal from an inverter) to achieve the same result of improved hysteresis and circuit stabilization during power state transitions.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and cancellation of claims 8-9, 12-13, and 16-22 of the ’674 patent as unpatentable.