Intel Corp v. Qualcomm Inc

1. Case Identification

• Case #: IPR2018-01334
• Patent #: 8,838,949
• Filed: July 3, 2018
• Petitioner(s): Intel Corporation
• Patent Owner(s): Patent Owner of U.S. Patent No. 8,838,949 to Gupta et al.
• Challenged Claims: 1-9 and 22-23

2. Patent Overview

• Title: Scatter Loading of Executable Software Image
• Brief Description: The ’949 patent discloses a method for "scatter loading" an executable software image in a multi-processor system. The technique involves a primary processor sending an image header and separate data segments to a secondary processor, which then uses information in the header to load the data segments directly from a hardware buffer into various locations in its system memory, avoiding an inefficient "double copy" process.

3. Grounds for Unpatentability

Ground 1: Obviousness over Bauer, Svensson, and Kim - Claims 1-9 and 22-23 are obvious over the combination of Bauer, Svensson, and Kim.

• Prior Art Relied Upon: Bauer (Application # 2006/0288019), Svensson (Patent 7,356,680), and Kim (Korean Patent Application Publication No. 10-2002-0036354).

• Core Argument for this Ground: Petitioner argued that the ’949 patent was allowed only after the applicant added limitations to distinguish it from the Svensson PCT reference. The key distinguishing features were: (1) the image header and data segments are received separately by the secondary processor, and (2) each data segment is scatter-loaded directly from the hardware buffer to system memory based on the header. Petitioner contended that Bauer and Kim, which were not before the examiner during prosecution, explicitly teach these allegedly novel features when combined with the baseline system architecture disclosed in Svensson. The combination of these references allegedly supplies the very elements the examiner previously found missing.

  • Prior Art Mapping: Petitioner asserted that Svensson disclosed the fundamental multi-processor system, including a primary processor (ARM CPU), a secondary processor (DSP), a non-volatile memory, and a hardware buffer (intermediate storage area) separate from the secondary processor’s system memory. However, Svensson taught a file format where each data block had its own header.

  Bauer, an explicit improvement on Svensson by the same inventors, was argued to teach a more efficient file format where a single header and a "section information" block precede all data segments. This structure contains the destination addresses for all subsequent data segments. Petitioner argued that modifying Svensson's system to use Bauer's more efficient file format was obvious. While Bauer's header itself does not contain the destination addresses (the separate "section information" block does), Petitioner contended it would have been an obvious design choice for a person of ordinary skill in the art (POSITA) to consolidate this information into the main header to meet the "image header" limitation as construed.

  Kim was presented to cure any alleged deficiency in Bauer and Svensson regarding the separate receipt of header and data. Kim explicitly disclosed a multi-processor loading method where "program block header information" is requested and received separately from, and prior to, the corresponding "program block" containing the actual program content. This directly maps to the ’949 patent’s limitation of receiving the image header and data segments separately. Dependent claims were argued to be obvious as they recited additional well-known features, such as implementing the system in a mobile phone (taught by Bauer and Svensson) or locating processors on different chips.

  • Motivation to Combine: A POSITA would combine Bauer and Svensson because Bauer was presented as a direct improvement on the file format used in the system described by Svensson, sharing inventors and assignees, and citing Svensson as a suitable program loader. The motivation to further combine this system with Kim's teachings stemmed from the need for memory efficiency, a key goal of Bauer. In systems with limited hardware buffer space unable to hold a large software image, Kim’s method of receiving and processing the header first allows the system to prepare for the incoming data segments and manage memory efficiently, avoiding the need to buffer the entire image at once. This directly addresses the problem of loading large images, which Bauer’s file format was designed to support (up to 4 GB).
  • Expectation of Success: A POSITA would have a high expectation of success. The combination involved applying a known data transfer protocol (Kim) to a known multi-processor architecture (Svensson) using an improved and compatible file format (Bauer). These were all well-established concepts in computer architecture, and their integration to achieve predictable benefits like improved loading efficiency and reduced memory requirements was considered straightforward.

4. Key Claim Construction Positions

• "image header" (claims 1, 4, 5, and 22): Petitioner proposed this term be construed as "a header associated with the entire image that specifies where the data segments are to be placed in the system memory." This construction was crucial because Bauer's header did not inherently contain destination addresses; they were in a separate "section information" block. Petitioner’s obviousness argument relied on the assertion that it would have been a simple and obvious modification for a POSITA to move the destination addresses from Bauer's "section information" block into Bauer's header to create the claimed "image header."

7. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-9 and 22-23 of the ’949 patent as unpatentable.