PTAB

IPR2018-01454

Cisco Systems Inc v. Centripetal Networks Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Network Protection Method and System
  • Brief Description: The ’148 patent discloses network protection devices, such as firewalls, that can be configured to process packets using a first rule set and subsequently reconfigured to use a second, different rule set. The technology aims to reduce latency and complexity when switching between rule sets, particularly in response to network threats.

3. Grounds for Unpatentability

Ground 1: Obviousness over Roese, Golnabi, Huima, and Hayter

  • Claims 1, 2, 4-10, 12-18, and 20 are obvious over Roese in view of Golnabi, Huima, and Hayter.
    • Prior Art Relied Upon: Roese (Application # 2006/0048142), Golnabi (a 2006 IEEE publication), Huima (Application # 2004/0015905), and Hayter (Patent 7,320,022).
    • Core Argument for this Ground:
      • Prior Art Mapping: Petitioner asserted that Roese serves as the primary reference, disclosing a "rapid response system" for network security that meets the core limitations of the challenged claims. Roese’s system processes packets using pre-installed rule sets and can be reconfigured to switch from a first rule set to a second rule set upon receiving a trigger signal. Petitioner argued that the remaining limitations are taught by the secondary references. Huima teaches pausing packet processing during a rule set update to avoid using outdated rules. Hayter teaches using multiple processors and caching unprocessed packets to improve performance and reduce latency. Golnabi teaches preprocessing firewall rules—by merging, separating, and reordering them—to optimize processing efficiency.
      • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would have been motivated to combine these references to improve the known firewall system of Roese. A POSITA would combine Roese with Golnabi to enhance rule processing efficiency, a known goal in firewall design. A POSITA would add Huima’s pausing feature to Roese’s system to further Roese's stated goal of rapid, effective response to threats by ensuring new rules are applied without delay. Finally, a POSITA would incorporate Hayter’s teachings on multi-processor architecture and caching to predictably reduce latency and increase throughput in Roese’s system.
      • Expectation of Success: Because the combination involved applying known, complementary techniques (rule optimization, update management, parallel processing) to a standard network firewall architecture, a POSITA would have had a reasonable expectation of success in creating a more efficient and responsive system.

Ground 2: Obviousness over Roese, Golnabi, Huima, Hayter, and Esbensen

  • Claims 3, 11, and 19 are obvious over Roese in view of Golnabi, Huima, Hayter, and Esbensen.
    • Prior Art Relied Upon: Roese (Application # 2006/0048142), Golnabi (a 2006 IEEE publication), Huima (Application # 2004/0015905), Hayter (Patent 7,320,022), and Esbensen (Patent 5,226,141).
    • Core Argument for this Ground:
      • Prior Art Mapping: This ground incorporated the combination from Ground 1 and added Esbensen to address limitations in dependent claims 3, 11, and 19, which require dynamically adjusting the size of a memory buffer based on the size of the rule set. Roese teaches storing rule sets in a cache or "memory buffer" but provides no implementation details. Petitioner asserted that Esbensen explicitly teaches a method for dynamically changing the size of a cache memory based on the size of the data to be stored within it.
      • Motivation to Combine: A POSITA implementing Roese’s system, particularly when combined with Golnabi’s rule-preprocessing techniques (which can alter the size of rule sets), would seek to optimize cache memory allocation. Esbensen provides a direct solution for this problem. A POSITA would be motivated to apply Esbensen's dynamic sizing method to Roese’s cache to avoid allocating excessive or insufficient memory, thereby improving the system's overall efficiency in a predictable manner.
      • Expectation of Success: Applying a known dynamic memory allocation technique from Esbensen to the caching function in Roese’s firewall system was a straightforward design choice for a POSITA, yielding the predictable benefit of improved memory management with a high expectation of success.

7. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’148 patent as unpatentable under 35 U.S.C. §103.