PTAB

IPR2018-01460

Apple Inc v. Qualcomm Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Local Interconnect Structures for High Density
  • Brief Description: The ’418 patent discloses electronic circuit implementations for high-density semiconductor devices. The technology addresses design challenges in sub-micron manufacturing by using blocking transistors and a multi-level local interconnect scheme, featuring "gate-directed" and "diffusion-directed" interconnects to achieve dense layouts while mitigating performance degradation.

3. Grounds for Unpatentability

Ground 1: Anticipation and Obviousness of Claims 1-3, 5, 8, 9, 12-14, and 16-19 over Rashed

  • Prior Art Relied Upon: Rashed (Patent 8,618,607).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Rashed anticipates every limitation of the challenged claims. Rashed discloses high-density integrated circuits with Field Effect Transistors (FETs) formed on a continuous active region, addressing similar layout problems as the ’418 patent. Petitioner asserted that Rashed’s "isolating electrodes," which are structurally identical to its gate electrodes and are used to electrically isolate adjacent transistors, function as and meet the limitations of the "blocking transistor" and its "first gate layer." Rashed also explicitly discloses multiple interconnect layers between the substrate and a "metal 1" layer, including structures that meet the definitions of the claimed "gate-directed" and "diffusion-directed" local interconnects.
    • Key Aspects: As an alternative, Petitioner argued that even if Rashed’s "metal 1" layer were not considered the "lower-most metal layer" as claimed, it would have been obvious to a person of ordinary skill in the art (POSITA) to interpret it as such or to implement Rashed’s teachings with the first metal layer being the lowest. This makes the claims obvious over Rashed for the same reasons they are anticipated.

Ground 2: Obviousness of Claims 4, 15, and 20 over Rashed in view of Lu

  • Prior Art Relied Upon: Rashed (Patent 8,618,607) and Lu (Patent 9,123,565).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addresses claims requiring the diffusion-directed local interconnect to be positioned within a footprint of the continuous diffusion region. Petitioner argued that Rashed teaches diffusion-directed interconnects (power rails 140H, 140L) located outside the active region footprint. Lu, which is directed to optimizing standard cell layouts, expressly teaches placing interconnects within the active regions to improve chip area utilization and regain gate density. The combination of Rashed’s high-density layout with Lu’s space-saving interconnect placement would result in the claimed configuration.
    • Motivation to Combine: A POSITA would combine Rashed with Lu to solve a known problem of inefficient chip area utilization. Lu’s technique of placing interconnects inside the active region is a direct solution to the layout inefficiency inherent in Rashed’s design, and applying it would predictably improve the density and efficiency of Rashed’s circuit, a shared objective of both references.
    • Expectation of Success: The proposed modification was argued to be a simple and predictable rearrangement of parts—relocating the power rails—using known layout techniques to achieve a well-understood benefit.

Ground 3: Obviousness of Claim 10 over Rashed in view of Nauta

  • Prior Art Relied Upon: Rashed (Patent 8,618,607) and Nauta (a 1992 IEEE journal article titled "A CMOS Transconductance-C Filter Technique for Very High Frequencies").
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addresses claim 10, which requires the "first gate layer" to be a gate layer for an "inverter." Petitioner argued that Rashed’s blocking transistor, while not an inverter, could be easily modified to function as one based on the teachings of Nauta. Nauta discloses a high-performance common-mode voltage inverter where the gate and drain terminals of the transistors are tied together. Petitioner showed how Rashed’s blocking transistor layout could be modified by shortening its gate lines and adding a simple diffusion-directed interconnect to connect the gate to the drain, thereby creating the inverter structure taught by Nauta.
    • Motivation to Combine: A POSITA would be motivated to implement Nauta’s efficient inverter design within Rashed’s high-density layout architecture. Nauta’s inverter was desirable for its good linearity, enhanced DC gain, and small footprint. Incorporating this known, advantageous circuit element into Rashed’s layout would predictably improve the circuit's functionality while maintaining high density.
    • Expectation of Success: The required modifications were asserted to be simple and routine for a POSITA, involving minor adjustments to the interconnect layout to apply a known circuit design (Nauta) to a known device layout (Rashed) to achieve a predictable result.

4. Key Claim Construction Positions

  • "means for coupling" (claims 17-19): Petitioner argued that under 35 U.S.C. §112(f), this term is a means-plus-function limitation. Based on the ’418 patent’s specification, Petitioner asserted that the structure corresponding to this function is a "diffusion-directed local interconnect." This construction was critical for mapping the diffusion-directed interconnects disclosed in Rashed (specifically, power rails 140H and 140L) to this claim element.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review (IPR) and the cancellation of claims 1-5, 8-10, and 12-20 of the ’418 patent as unpatentable.