PTAB

IPR2018-01484

Everlight Electronics Co Ltd v. Bridgelux Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Efficient LED Array
  • Brief Description: The ’051 patent discloses a method for forming a light-emitting diode (LED) apparatus by mounting a plurality of LED chips directly onto a reflective metal substrate. The design is intended to improve thermal dissipation and light reflectivity compared to prior art methods using ceramic substrates.

3. Grounds for Unpatentability

Ground 1: Claims 1-7 are anticipated by Ostler

  • Prior Art Relied Upon: Ostler (Patent 6,954,270).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ostler discloses every limitation of the challenged claims. Ostler teaches a method of forming an LED-based forensic light by mounting an array of GaN LED chips directly onto a metal heat sink made of copper, aluminum, or silver. This heat sink serves as the claimed "metal substrate." Ostler further teaches that the heat sink surface can be polished or coated to be reflective and that the LED chips are spaced apart by one millimeter or more, which satisfies the "at least 0.5 millimeters" spacing limitation of claim 1. Dependent claims are also met, as Ostler discloses using polished aluminum (claim 2) or silver (claim 3) for the reflective surface, which inherently provides reflectivity greater than 70% (claim 4). The structure also provides separate thermal (through the heat sink) and electrical (via top-surface wire bonds) paths (claims 5-6) and teaches mounting the substrate directly to another heat sink (claim 7).

Ground 2: Claims 1-7 are anticipated by Sanpei

  • Prior Art Relied Upon: Sanpei (EP Patent Publication No. 1 895 602).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Sanpei teaches an LED array that anticipates all challenged claims. Sanpei discloses mounting multiple nitride-based LED chips directly onto a metal baseboard (e.g., aluminum or copper) that is configured with a reflective layer of silver plating. This configuration directly maps to the claim 1 limitations of a metal substrate with a reflective surface and direct mounting for thermal dissipation. Sanpei’s figures show significant spacing between the LED chips to allow light to reflect from the surface, which Petitioner contended meets the 0.5 mm limitation. Sanpei also explicitly teaches a reflectivity of "preferably 70% or more" (claim 4), using silver plating (claim 3), providing separate thermal and electrical paths (claim 5), using chips with top-side contacts (claim 6), and mounting the metal substrate to a heat sink (claim 7).

Ground 3: Claims 1-7 are obvious over Baek and Ostler

  • Prior Art Relied Upon: Baek (Application # 2007/0075325) and Ostler (Patent 6,954,270).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Baek discloses every limitation of the challenged claims except for an explicit chip spacing of at least 0.5 mm. Baek teaches an array of GaN LED chips mounted directly to a reflective surface of a metal substrate (e.g., copper) to improve heat dissipation. The reflective surface can be silver-plated, which provides the required high reflectivity. Baek’s design inherently creates separate thermal and electrical paths. While Baek teaches spacing the chips apart in recesses to prevent light interference, it does not specify a distance of at least 0.5 mm. Ostler remedies this by expressly teaching a chip spacing of one millimeter or more for the same purpose of creating a thermally efficient LED array.
    • Motivation to Combine: A POSITA would combine Baek and Ostler because both references address the same problem of designing thermally efficient LED arrays with high light output. A POSITA would have recognized Ostler's specific teaching on chip spacing as a known, beneficial technique directly applicable to Baek's similar array. Applying Ostler's spacing would have been a simple design choice to predictably improve Baek’s thermal performance and reflectivity.
    • Expectation of Success: A POSITA would have reasonably expected success in applying Ostler’s spacing to Baek's array. The combination would only require setting the known spacing of chips in Baek's design to a specific, proven distance disclosed in Ostler, using conventional and predictable design methods to achieve the desired improvements.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1-7 are obvious over Ostler and Sanpei (Ground 3), claims 1-7 are obvious over Sanpei and Ostler (Ground 4), and claim 4 is obvious over Baek, Ostler, and Sanpei (Ground 6). These grounds relied on similar rationales, primarily arguing that if one reference was found to be missing a specific limitation (e.g., chip spacing or reflectivity percentage), the other references explicitly taught that feature as a solution to the same technical problem.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-7 of the ’051 patent as unpatentable.