PTAB

IPR2018-01603

Microsoft Corp v. Saint Regis Mohawk Tribe

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1. Case Identification

2. Patent Overview

  • Title: Multi-Adaptive Processing Systems and Techniques for Enhancing Parallelism and Performance of Computational Functions
  • Brief Description: The ’324 patent describes a method for data processing using a reconfigurable computing system, such as one with Field Programmable Gate Arrays (FPGAs). The method involves processing a "systolically implemented" calculation where different "data dimensions" are processed concurrently by "systolically linked lines of code" that are instantiated as clusters of functional units.

3. Grounds for Unpatentability

Ground 1: Claims 1, 18, 21, and 22 are anticipated by or, in the alternative, obvious over Splash2.

  • Prior Art Relied Upon: Splash2 (a 1996 book titled "Splash 2, FPGAs in a Custom Computing Machine").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Splash2, a book describing a well-known reconfigurable computer system from the 1990s, discloses every element of the challenged claims. Splash2 describes implementing a genetic sequence comparison algorithm (the "Edit Distance Algorithm") on its FPGA-based hardware. This method involves transforming the algorithm into a calculation that is systolically implemented, as data flows rhythmically between processing elements (PEs) without a central clock driving data movement, consistent with the patent's definition of "systolic." The PEs are instantiated as needed on the FPGAs, and different PEs concurrently process different data dimensions (e.g., one PE compares a source character to a stream of target characters while another PE does the same for the next source character). Dependent claims were also allegedly met, as the algorithm is a "search algorithm for data mining" (claim 18), a "genetic pattern matching function" (claim 21), and useful for "protein folding" applications (claim 22).
    • Motivation to Combine (for §103 grounds): As an alternative, Petitioner argued that even if not directly taught, it would have been obvious to implement the systolic algorithms of Splash2's Chapter 8 on the hardware system described in its Chapters 1-6. The motivation was clear, as the book explicitly states this implementation was done to achieve advantageous high-speed performance for genetic sequence processing, a well-known goal at the time.
    • Expectation of Success (for §103 grounds): A person of ordinary skill in the art (POSITA) would have had a high expectation of success, as the book itself documents the successful implementation and its superior performance results.

Ground 2: Claims 1, 18, 21, and 22 are obvious over Splash2 in view of Gaudiot.

  • Prior Art Relied Upon: Splash2 (a 1996 book) and Gaudiot (a 1987 IEEE article on data-driven multicomputers).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground supplements Splash2 to the extent it is found not to explicitly teach a "systolic" implementation that is "transport triggered" and operates "without a program counter or clock that drives the movement of data," per the patentee's definition during prosecution. Gaudiot taught data-driven multiprocessor systems where operations are scheduled based on the availability of operands, and data movement is triggered by the arrival of data, not by a clock.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Splash2's systolic array architecture with Gaudiot's data-driven techniques to improve efficiency and scalability. Gaudiot expressly taught that data-driven approaches solve "crucial scheduling problem[s]" in systems with many processors and allow for maximum parallelism without a central controller, directly addressing the challenges of implementing complex algorithms like those in Splash2.
    • Expectation of Success (for §103 grounds): Success was expected because the use of data-driven techniques in systolic arrays was known in the prior art, and the combination represented the application of a known processing paradigm (Gaudiot) to improve a known system (Splash2).

Ground 3: Claims 2-5, 22, and 23 are obvious over Splash2 (with or without Gaudiot) in view of Roccatano.

  • Prior Art Relied Upon: Splash2 (a 1996 book), Gaudiot (a 1987 article), and Roccatano (a 1998 journal article on parallel molecular dynamics).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed dependent claims reciting specific types of "data dimensions." Roccatano described a program for simulating molecular dynamics on a parallel computer using a systolic loop. This simulation inherently involves processing different "data dimensions" that comprise multiple vectors (atomic position vectors, claim 2), multiple planes (in 2D or 3D simulations, claim 3), multiple time steps (simulating dynamics over time, claim 4), and multiple grid points (atom locations, claim 5). Roccatano also taught simulating the BPTI protein, satisfying the "protein folding function" (claim 22) and "organic structure interaction function" (claim 23) limitations.
    • Motivation to Combine (for §103 grounds): A POSITA would have been motivated to implement Roccatano's molecular dynamics algorithms on the high-performance Splash2 system. Splash2 was explicitly promoted for achieving "supercomputer performance" in applications including molecular biology, the exact field of Roccatano. By 2002, using parallel computing for molecular dynamics was popular, and a POSITA would have sought to apply a powerful, known hardware platform like Splash2 to a known, computationally intensive problem like the one described in Roccatano to achieve predictable performance gains.
    • Expectation of Success (for §103 grounds): Success was expected because this combination represented the use of a known high-performance computing system (Splash2) for its intended purpose (molecular biology applications) with a known algorithm (Roccatano), which is a predictable application of prior art elements.

4. Key Claim Construction Positions

  • "systolic": Petitioner argued this term should be construed according to the definition the patentee provided during prosecution to overcome prior art rejections. This definition states a systolic array is an arrangement of data processing units operating "without a program counter or clock that drives the movement of data," where the operation is "transport triggered, i.e., by the arrival of a data object." This construction was central to mapping Splash2 and Gaudiot to the claims while distinguishing over prior art that relied on system clocks.
  • "transforming an algorithm into a calculation that is systolically implemented": Petitioner proposed this phrase means "compiling an algorithm into configuration code representing computations that process data in a systolic fashion." This construction was based on documents incorporated by reference into the ’324 patent and was used to argue that the process of compiling VHDL code to configure the FPGAs in Splash2 met this claim limitation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-5, 18, and 21-23 of the ’324 patent as unpatentable.