PTAB

IPR2018-01604

Microsoft Corp v. Saint Regis Mohawk Tribe

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Switch/Network Adapter Port for Clustered Computers Employing a Chain of Multi-Adaptive Processors in a Dual In-Line Memory Module Format
  • Brief Description: The ’524 patent describes a processor element, intended for use as a network adapter, that plugs into a standard memory module slot (e.g., a DIMM slot) on a computer’s motherboard. The element uses a Field Programmable Gate Array (FPGA) to process data received from the memory module bus and provide it to an external device, aiming to offer higher bandwidth and lower latency than traditional PCI-based adapters.

3. Grounds for Unpatentability

Ground 1: Anticipation by Tsutsui - Claims 1, 2, 13-15 are anticipated by Tsutsui

  • Prior Art Relied Upon: Tsutsui ("YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing," a 1997 publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Tsutsui discloses the YARDS system, an architecture for telecommunication data processing that anticipates every limitation of the challenged claims. The YARDS system is a "computer system" with a microprocessor (MPU) and memory modules (SIMMs). Tsutsui’s array of FPGAs functions as the claimed "processor element." These FPGAs are connected to a "Local Bus," which serves as the "memory module bus" by connecting to the SIMMs. The FPGAs are disclosed as being configurable to perform algorithms like re-shaping data, thus meeting the "operative to alter data" limitation. The "direct data connection" for providing altered data to an "external device" is disclosed in Tsutsui's VME bus interface, which connects the FPGAs via the Local Bus to other YARDS systems or host computers. Dependent claims 2, 13, 14, and 15 were also argued to be anticipated by features inherent in the YARDS architecture, such as interrupt signals for control (claim 2) and connections to other computer systems (claim 13).

Ground 2: Obviousness over Tsutsui in view of Tsutsui II - Claims 1, 2, 13-15 are obvious over Tsutsui in view of Tsutsui II

  • Prior Art Relied Upon: Tsutsui, and Tsutsui II ("Special purpose FPGA for High-Speed Digital Telecommunication Systems," a 1995 publication).

  • Core Argument for this Ground:

    • Prior Art Mapping: To the extent Tsutsui is found not to explicitly teach an FPGA that is "operative to alter data" as claimed, Tsutsui II remedies this deficiency. Tsutsui II, co-authored by some of the same researchers as Tsutsui, describes the PROTEUS FPGA specifically designed for ATM transport data processing. This processing includes "scrambling," a technique that transforms bit patterns to aid synchronization, which Petitioner contended is a form of "altering data." Combining the teachings would result in using the PROTEUS FPGAs from Tsutsui II within the YARDS system of Tsutsui to perform scrambling on ATM data.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references for several reasons. Tsutsui explicitly cites Tsutsui II as disclosing the "original FPGA" designed for the high-speed telecommunication processing that is the focus of the YARDS system. The references are analogous art from the same research team addressing the same technical problems. Tsutsui II’s description of scrambling as an "essential operation for transport data" would have motivated a POSITA to incorporate this function into the YARDS system to improve its performance for ATM applications.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in combining the references. The combination involved implementing a known data processing function (scrambling) from Tsutsui II in a compatible system architecture (Tsutsui), which was a predictable application of known technologies.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claim 2 is obvious over Tsutsui in view of Stone (a textbook on microcomputer interfacing) for teaching conventional interrupt signaling. Claim 14 is obvious over Tsutsui in view of Collins (Patent 5,671,355) for teaching the configuration of FPGAs as processors that can run software. Claim 15 is obvious over Tsutsui in view of Hayashi (a 1995 publication) for teaching the complementary function of descrambling incoming data.

4. Key Claim Construction Positions

  • "providing said altered data directly from said memory module bus to an external device coupled thereto": This phrase was the central point of dispute. Petitioner argued that the prosecution history creates a clear estoppel, requiring the term to be construed as a direct transfer of data from the memory bus to the external device without an intermediate memory buffer. During prosecution, the applicant amended the claim by moving the word "directly" to overcome a rejection based on the Klingelhofer prior art, which used a VRAM as a temporary buffer. The applicant explicitly stated the amendment was intended to add a "positive reciting" of a "direct transfer of data from the memory module bus to the external device," thereby disclaiming systems with intermediate storage.
  • "memory module bus": Petitioner argued this term should be construed according to its plain meaning as "a bus used to communicate with a memory module." Petitioner contended that any attempt by the Patent Owner to import a "high transfer rate" limitation is improper, as it is not supported by the claim language or specification.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review (IPR) and cancellation of claims 1, 2, 13-15 of the ’524 patent as unpatentable.