PTAB

IPR2019-00053

ARM Ltd v. Complex Memory LLC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Dynamic Random Access Memory (DRAM) with Integral Static Random Access Memory (SRAM)
  • Brief Description: The ’195 patent describes a memory system, such as a DRAM, that includes an integral SRAM. This integral SRAM functions as a cache to provide faster data access compared to the main DRAM array.

3. Grounds for Unpatentability

Ground 1: Claims 6 and 8 are obvious over Fukuda in view of Lin.

  • Prior Art Relied Upon: Fukuda (Patent 5,619,676) and Lin (Patent 5,423,019).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Fukuda disclosed the conceptual framework for a memory system with a cache, including all core operations recited in claim 6. Fukuda taught a memory cell array (main memory) and associated cache memories, along with the logic for handling cache hits, cache misses, and prefetching. However, Fukuda did not specify the underlying memory technology. Lin supplied this missing detail, explicitly teaching the use of DRAM for main memory and separate SRAM arrays for cache tag memory and cache data memory. Petitioner contended that in the combined system, Fukuda’s memory array corresponded to the claimed "memory array," while Lin’s cache data SRAM corresponded to the "plurality of registers" and Lin's cache tag SRAM corresponded to the "plurality of latches." The prefetching mechanism in Fukuda, which modifies a current address to predict and fetch a subsequent block of data, was alleged to teach the "modifying the received address" limitation. For claim 8, Petitioner argued that serial access of registers was a well-known and inherent mode of operation.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references because both aimed to improve cache memory performance. A POSITA implementing Fukuda’s high-level architecture would have naturally looked to a reference like Lin to select from the finite, well-known memory structure options (DRAM, SRAM) to build the system, as this would be a mere application of known techniques to yield predictable results.
    • Expectation of Success: A POSITA would have a high expectation of success in using the common DRAM and SRAM structures from Lin to implement the cache system of Fukuda, as such components were standard and their integration was well understood.

Ground 2: Claim 7 is obvious over Fukuda and Lin in view of Matsuda.

  • Prior Art Relied Upon: Fukuda (Patent 5,619,676), Lin (Patent 5,423,019), and Matsuda (Patent 5,509,132).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the Fukuda/Lin combination to address the additional limitation of claim 7: "accessing a plurality of locations in the register in response to a plurality of column addresses." While the primary combination established the SRAM-based register, it did not explicitly detail the addressing mechanism. Matsuda was introduced to supply this teaching, as it expressly disclosed that an SRAM memory array is accessed via a "column address signal."
    • Motivation to Combine: A POSITA building the Fukuda/Lin system would be motivated to consult a reference like Matsuda for low-level implementation details. Since accessing SRAM via column addresses was a standard and well-known technique, its application to the SRAM-based cache of the primary combination was a predictable design choice.

Ground 3: Claims 6 and 8 are obvious over Smith in view of Horowitz.

  • Prior Art Relied Upon: Smith (Alan Smith, Cache Memories, Computing Surveys (Sep. 1982)) and Horowitz (Paul Horowitz and Winfield Hill, The Art of Electronics, Second Edition (1989)).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted this ground as an alternative combination based on foundational prior art. Smith, a seminal paper, provided the complete conceptual basis for cache memory operations, including the use of main memory, cache address and data arrays, cache hits, cache misses, and prefetching by incrementing an address ("one block lookahead"). Horowitz, a standard textbook, taught the common knowledge that memory systems were built from a finite set of interchangeable components like RAMs, registers, and latches. Petitioner argued a POSITA would implement the conceptual system of Smith by using the standard components described in Horowitz: a RAM for the main "memory array," registers for the cache data array ("plurality of registers"), and latches for the cache address array ("plurality of latches").
    • Motivation to Combine: A POSITA would be motivated to combine the teachings because Smith described a conceptual system and Horowitz provided the well-known, off-the-shelf components to realize it. This combination represented a simple substitution of one known, interchangeable element for another to obtain a predictable result.

Ground 4: Claim 7 is obvious over Smith and Horowitz in view of Matsuda.

  • Prior Art Relied Upon: Smith (Computing Surveys (Sep. 1982)), Horowitz (The Art of Electronics (1989)), and Matsuda (Patent 5,509,132).
  • Core Argument for this Ground:
    • Prior Art Mapping: Similar to Ground 2, this ground added Matsuda to the primary Smith/Horowitz combination to explicitly teach the "column addresses" limitation of claim 7. Matsuda provided the specific, low-level detail of using column address signals to access the SRAM-based registers established by the Smith/Horowitz combination.
    • Motivation to Combine: The motivation was identical to Ground 2: a POSITA implementing the cache system disclosed by Smith and Horowitz would naturally refer to a reference like Matsuda for standard, well-known addressing mechanisms to achieve a predictable result.

4. Key Claim Construction Positions

  • "exchanging": For the purposes of the IPR, Petitioner adopted the Patent Owner's apparent interpretation from related litigation. Under this interpretation, "exchanging data" (recited in claim 6) was construed to describe the process that occurs after a "cache miss," where requested data is fetched from the main memory array and used to update (i.e., replace or evict existing data in) the SRAM registers and latches.

5. Key Technical Contentions

  • Interchangeability of Memory Terms: A central technical argument was that a POSITA would have understood the terms "registers," "latches," and "RAMs" (including SRAMs) to be largely interchangeable for the purposes of building a cache memory. Petitioner argued that these components perform the same basic function of holding bits and were well-known, finite options for memory implementation. This contention was used to justify combining references and mapping terms like "cache data SRAM" to the claimed "plurality of registers."

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 6-8 of Patent 5,890,195 as unpatentable under 35 U.S.C. §103.